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data sheet, v1.0, feb 2005 TC1115 32-bit single-chip microcontroller advance information microcontrollers never stop thinking.
edition 2005-02 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in lif e-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet, v1.0, feb 2005 TC1115 32-bit single-chip microcontroller advance information microcontrollers never stop thinking.
controller area network (can): license of robert bosch gmbh TC1115 data sheet advance information revision history: 2005-02 v1.0 previous version: none page subjects (major cha nges since la st revision) we listen to your comments any information within this do cument that you feel is wron g, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to th is document) to: mcdocu.comments@infineon.com
TC1115 table of contents page data sheet i-1 v1.0, 2005-02 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 pin definitions and func tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 on-chip memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 memory protection system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 protection for direct translat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.2 protection for pte based tran slation . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.3 memory checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 on-chip bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.1 local memory bus (lmb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.2 flexible peripheral interco nnect bus (fpi) . . . . . . . . . . . . . . . . . . . . . . 27 3.4.3 lfi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5 lmb external bus unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.6 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.8 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.9 asynchronous/synchronous seri al interface (asc) . . . . . . . . . . . . . . . . . 36 3.10 high-speed synchro nous serial interface (ssc) . . . . . . . . . . . . . . . . . . . 39 3.11 inter ic serial interface (iic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.12 multican . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.13 micro link serial bus interfac e (mli) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.14 general purpose timer unit (gptu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.15 capture/compare unit 6 (ccu6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.16 system timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.17 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.18 system control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.19 boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.20 power management system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.21 on-chip debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.22 clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.23 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.24 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.25 identification register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.1.1 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
TC1115 table of contents page data sheet i-2 v1.0, 2005-02 4.1.2 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.1.3 operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.1 input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.3 iic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.2.4 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.1 power, pad and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.2 pll parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.3.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.3.4 input clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.3.5 port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.3.6 timing for jtag signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.3.7 timing for ocds trace and breakpoint signals . . . . . . . . . . . . . . . . . . 84 4.3.8 ebu timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.3.8.1 sdclko output clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.3.8.2 bfclko output clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.3.8.3 timing for sdram access signals . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.3.8.4 timing for burst flash ac cess signals . . . . . . . . . . . . . . . . . . . . . . . 88 4.3.8.5 timing for demultiplexed access signals . . . . . . . . . . . . . . . . . . . . . 90 4.3.8.6 timing for multiplexed ac cess signals . . . . . . . . . . . . . . . . . . . . . . . 92 4.3.9 peripheral timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3.9.1 ssc master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3.9.2 mli interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
data sheet 1 v1.0, 2005-02 TC1115 32-bit single-chip microcontroller tricore? family advance information 1 summary of features ? high performance 32-bit tricore? v1.3 cpu with 4-stage pipeline ? floating point unit (fpu) ? dual issue super-sca lar implementation ? mac instruction maximum triple issue ? circular buffer and bit-reverse add ressing modes for dsp algorithms ? very fast interrupt response time ? hardware controlled context switch for task switch and interrupts ? memory management unit (mmu) ? on-chip memory ? 28-kbyte data memory (spram) ? 32-kbyte code memory (spram) ? 16-kbyte instruction cache (icache) ? 4-kbyte data cache (dcache) ? 64-kbyte sram data memory unit (dmu) ? 16-kbyte boot rom ? on-chip bus systems ? 64-bit high performance local memory bu s (lmb) for fast a ccess betw een caches and on-local memories and fpi interface ? on-chip flexible peripheral interconn ect bus (fpi) for interconnections of functional units ? dma controller with 8 channel s for data transfer operatio ns between peripheral units and memory locations ? two high speed micro link interfaces (mli0/1) for controller communication and emulation ? flexible external bus inte rface unit (ebu) to acce ss external data memories ? one multifunctional general purpose timer unit (gptu) with three 32-bit timer/ counters ? two capture and compare units (ccu60/1) for pwm signal gene ration, each with ? 3-channel, 16 bit capt ure and compare unit ? 1-channel, 16 bi t compare unit ? three asynchronous/synchronous serial channels (asc0/1/2) with baud-rate generator, parity, framing an d overrun error detection, su pport fifo and irda data transmission ? two high speed synchronous serial channels (ssc0/1) with programmable data length, fifo support and shift direction
TC1115 summary of features data sheet 2 v1.0, 2005-02 advance information ? one multican module with four can nodes and 128 message buffers for high efficiency data handling ? inter-ic (iic) module wi th two physical iic buses ? digital i/o ports with 3.3 v i/o capabilities ? level 2 on-chip debug support ? power management system ? clock generation unit with pll ? maximum cpu and bus clock frequency at 150 mhz without mm u and 120 mhz with mmu ? ambient temperature under bias: -40 to +85c ? p-lbga-208 package
TC1115 general device information data sheet 3 v1.0, 2005-02 advance information 2 general device information 2.1 block diagram figure 2-1 TC1115 block diagram cedar_blk _TC1115 bo ot -ro m 16 kby tes asc0 fifo, ir da asc1 fifo, irda asc2 fifo, ird a ss c0 s sc1 iic 2 ch an nel s scu (pwr) po wer management, wa tchd og t i m er, re set sbc u fp i b us ce r be r us jt ag pll tricore tm 1m cp u fpu ocds pmi (program memory interface) 3 2 kb scr at ch pad ram 16 kb i nst ru ctio n cac he dmu 64 kb sram j tag i/o xtal2 xtal1 5 co nt ro l brkout brkin 7 ocds 2 16 2 dmi (da t a m emory interface) 2 8 kb sc ra tc h pa d ram 4 kb d at a ca ch e lb cu lm b bus lfi brid ge 2 2 2 8 3 4 port0 port1 port2 port3 port4 mm u lmb (local memory bus) 64 bit ext er na l in te rr up ts 12 8 64 v dd 1 .5- 3.3 v v ss t c1115 bloc k diagr am stm mult ican 4 nod es dma 8 c han ne l s gp tu 3 t im er s ccu6 c cu6 1 ccu60 m li1 mli 0 mem checker 2 8 411 2 2 13 16 16 16 16 8 8 3 6 3 3 8 8 8 cps eb u 32 23 ad[3 1:0 ] eb u_control 24 a[2 3:0 ] 3 1 1 1 1 1 fp i bu s ( f lex ib le per ip he ra l i nt er f ace ), 32 bit dma bu s , 3 2 bi t sm if
TC1115 general device information data sheet 4 v1.0, 2005-02 advance information 2.2 logic symbol figure 2-2 TC1115 logic symbol mcb04945mod_TC1115 port 0 16-bit wai t rd/wr rd hwcfg[0:2] nmi hdrst porst v ss v ddosc3 ras al e ebu control alternate functions digital circuitry po we r su p p ly 3 general cont rol cas cs[0:3] 4 cscomb sdcl ki cke mr / w bfcl ki baa adv sdclko n.c. xtal 1 xtal 2 v ssosc3 oscillator 14 6 v dd v ddp 9 tdi tck trst a[0:23] bc[0:3] ad[0:31] port 1 16-bit port 2 16-bit port 3 16-bit port 4 8-bit gptu, multican, ssc0/1, asc1/2, ccu60, mli0, ebu, scu, external interrupts ssc0/1, multican, ebu, scu, ocds asc0/1/2, ssc0/1, iic, ccu60, ebu, scu ssc0/1, ccu61, mli1, ocd s tdo ocds / jtag control mli0, scu bfcl ko TC1115 tms brki n trclk v ddosc v ssosc 4 5
TC1115 general device information data sheet 5 v1.0, 2005-02 advance information 2.3 pin configuration figure 2-3 TC1115 pins: p-bga-208 package (top view) mcp04950mod_TC1115 abcdefg hj p2 . 7 klmn v dd osc3 pr v ss t reser ved p3 . 1 0 16 15 p0 . 9 p0 . 1 14 p1 . 1 0 16 15 14 13 v ss 13 12 11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 12 reser ved reser ved abcd efghj klmn pr t v ss v dd v dd v dd v ss v ss v dd v dd v dd v ss v ss v dd v ss v ss v dd p3 . 1 1 p3 . 1 2 p2 . 1 5 p2 . 1 4 p2 . 1 1 p2 . 9 p2 . 8 v ddosc xtal 1 xtal 2 n.c. p2 . 4 p0 . 3 v ss p2 . 1 2 p3 . 1 5 p3 . 9 p3 . 5 p3 . 6 p3 . 3 p3 . 2 p3 . 8 p3 . 0 p3 . 1 p1 . 9 p1 . 1 1 p1 . 1 4 p1 . 1 3 p1 . 1 5 p3 . 4 p3 . 7 p3 . 1 4 p2 . 1 3 hw cfg1 hw cfg0 p2 . 5 p2 . 3 p0 . 1 0 n.c. td i p0 . 8 p2 . 2 v ddp v ss p2 . 1 0 p3 . 1 3 v ddp v ss v dd p1 . 1 2 v ddp p1 . 8 p1 . 7 p1 . 5 p1 . 6 p1 . 3 p1 . 1 p1 . 2 baa ad v p1 . 4 p1 . 0 a1 7 a1 8 a1 9 a2 0 a1 6 wai t cs2 cs0 cs1 ad 0 cs3 a1 5 bc 3 ad 1 bc 2 ad1 6 bc 1 ad 2 ad 3 ras bc0 ad 1 7 ad 4 cas ad 1 8 ad 1 9 ad 2 0 v ddp ad 5 ad 2 1 ad 7 ad 2 5 ad 6 ad 2 2 ad 8 ad 9 reser ved ad 2 3 ad 2 4 bfcl ki ad 2 8 ad 2 9 a1 4 cke v ddp a2 3 a2 2 v ddp v ss v ss a2 1 v ss tc k p0 . 5 p2 . 0 p2 . 6 p0 . 0 tr st p0 . 4 p4 . 3 hw cfg2 p4 . 6 p4 . 4 td o p0 . 6 p0 . 2 p0 . 7 p0 . 1 1 tms p4 . 1 p0 . 1 2 p0 . 1 4 trclk p4 . 0 p0 . 1 3 p4 . 2 nmi p4 . 5 p0 . 1 5 hdrst p4 . 7 po r st br ki n ad 1 1 ad 1 2 ad 1 5 ad 3 0 a1 0 a1 1 a1 2 a1 3 cs comb mr /w al e rd/wr ad 2 6 ad 2 7 ad 3 1 ad 1 4 a5 a6 a7 a8 a9 rd vss vss a3 n.c. a4 a2 a1 a0 sdcl ko ad 1 3 ad 1 0 bfcl ko 208-pin p-lbga package pin configuration (top view) for TC1115 v ss p2 . 1 sdcl ki
TC1115 general device information data sheet 6 v1.0, 2005-02 advance information 2.4 pin definitions and functions table 2-1 pin definitions and functions symbol pin in out pu/ pd 1) functions p0 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.11 n11 p15 p10 m15 r11 r12 r10 n10 r13 r15 r14 n9 i/o i/o i/o i/o o i/o i/o i/o o i/o i o i/o i i o i/o i/o i o i/o o i i o o i i i i o o i o puc puc puc puc puc puc puc puc puc puc puc puc port 0 port 0 is a 16-bit bi-directi onal general purpose i/o port which can be alternativel y used for gptu, multican, asc1/2, ssc0/1, mli0, ebu and scu. gptu_0 gptu input/output line 0 rxd1b asc1 receiver input/output b gptu_1 gptu input/output line 1 txd1b asc1 transmitter output b gptu_2 gptu input/output line 2 rxd2b asc2 receiver input/output b gptu_3 gptu input/output line 3 txd2b asc2 transmitter output b gptu_4 gptu input/output line 4 slsi1 ssc1 slave select input breq ebu bus request output gptu_5 gptu input/output line 5 hold ebu hold request input cc60_t12hr ccu60 time r 12 hardware run brkout _b ocds break out b gptu_6 gptu input/output line 6 hlda ebu hold ackn owledge input/output cc60_t13hr ccu60 time r 13 hardware run slso0_0 ssc0 slave select output 0 gptu_7 gptu input/output line 7 slso1_0 ssc1 slave select output 0 rxdcan0_a can node 0 receiver input a req0 external trigger input 0 tclk0a mli0 transmit channel clock output a txdcan0_a can node 0 tr ansmitter output a tready0a mli0 transmit channel ready input a req1 external trigger input 1 rxdcan1_a can node 1 receiver input a req2 external trigger input 2 tvalid0a mli0 transmit channel valid output a txdcan1_a can node 1 tr ansmitter output a req3 external trigger input 3 tdata0a mli0 transmit channel data output a
TC1115 general device information data sheet 7 v1.0, 2005-02 advance information p0.12 p0.13 p0.14 p0.15 p9 p8 n8 p7 i i i o i o i i i o i i puc puc puc puc rxdcan2 can node 2 receiver input rclk0a mli0 receive channel clock input a req4 external trigger input 4 txdcan2 can node 2 transmitter output req5 external trigger input 5 rready0a mli0 receive channel ready output a rxdcan3 can node 3 receiver input req6 external trigger input 6 rvalid0a mli0 receive channel valid input a txdcan3 can node 3 transmitter output req7 external trigger input 7 rdata0a mli0 receive channel data input a p1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 d11 c12 d12 b12 c11 c13 a12 i/o i i o i o o i i o o i o i o i o i o puc puc puc puc puc puc puc port 1 port 1 serves as 16-bit bi-d irectional ge neral purpose i/o port which can be us ed for input/output for multican, can, ocds l2, ssc0/1, ebu and scu. rxdcan0_b can node 0 receiver input b swcfg0 software configuration 0 ocdsa_0 ocds l2 debug line a0 swcfg1 software configuration 1 txdcan0_b can node 0 tr ansmitter output b ocdsa_1 ocds l2 debug line a1 rxdcan1_b can node 1 receiver input b swcfg2 software configuration 2 ocdsa_2 ocds l2 debug line a2 txdcan1_b can node 1 tr ansmitter output b swcfg3 software configuration 3 ocdsa_3 ocds l2 debug line a3 swcfg4 software configuration 4 ocdsa_4 ocds l2 debug line a4 swcfg5 software configuration 5 ocdsa_5 ocds l2 debug line a5 swcfg6 software configuration 6 ocdsa_6 ocds l2 debug line a6 table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 8 v1.0, 2005-02 advance information p1.7 p1.8 p1.9 p1.10 p1.11 p1.12 p1.13 p1.14 p1.15 b13 a13 a14 b14 c14 f13 e14 d14 f14 i o i o i o i o i o o i o o i o o o i o i o i o puc puc puc puc puc puc puc puc puc swcfg7 software configuration 7 ocdsa_7 ocds l2 debug line a7 swcfg8 software configuration 8 ocdsa_8 ocds l2 debug line a8 swcfg9 software configuration 9 ocdsa_9 ocds l2 debug line a9 swcfg10 software configuration 10 ocdsa_10 ocds l2 debug line a10 swcfg11 software configuration 11 ocdsa_11 ocds l2 debug line a1 slso0_1 ssc0 slave select output 1 swcfg12 software configuration 12 ocdsa_12 ocds l2 debug line a12 slso1_1 ssc1 slave select output 1 swcfg13 software configuration 13 ocdsa_13 ocds l2 debug line a13 slso0_2 ssc0 slave select output 2 slso1_2 ssc1 slave select output 2 swcfg14 software configuration 14 ocdsa_14 ocds l2 debug line a14 slsi0 ssc0 slave select input rmw ebu read modify write swcfg15 software configuration 15 ocdsa_15 ocds l2 debug line a15 table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 9 v1.0, 2005-02 advance information p2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2.10 p2.11 p2.12 p12 p11 p13 p14 n15 n14 n12 k16 j16 h16 l13 g16 k15 i/o i/o o o i i/o i/o i/o o i/o i/o i/o o i/o i/o i/o o o i/o i/o o o i/o i o puc puc puc puc puc puc puc puc puc puc puc puc ? port 2 port 2 is a 16-bit bi-directi onal general purpose i/o port which can be alternatively us ed for asc0/1/2, ssc0/1, ccu60, iic, ebu and scu. rxd0 asc0 receiver input/output line csemu ebu chip select output for emulator region txd0 asc0 transmitter output line testmode test mode select input mrst0 ssc0 master receive/slave transmit input/output mtsr0 ssc0 master tr ansmit/slave receive input/output sclk0 ssc0 clock input/output line cout60_3 ccu60 compar e channel 3 output mrst1a ssc1 master receive/slave transmit input/output a cc60_0 ccu60 input/output of capture/ compare channel 0 mtsr1a ssc1 master tr ansmit/slave receive input/output a cout60_0 ccu60 output of capture/compare channel 0 sclk1a ssc1 clock input/output line a cc60_1 ccu60 input/output of capture/ compare channel 1 rxd1a asc1 receiver input/output line a cout60_1 ccu60 output of capture/compare channel 1 txd1a asc1 transmit ter output line a cc60_2 ccu60 input/output of capture/ compare channel 2 rxd2a asc2 receiver input/output line a cout60_2 ccu60 output of capture/compare channel 2 txd2a asc2 transmit ter output line a sda0 iic serial data line 0 ctrap0 ccu60 trap input slso0_3 ssc0 slave select output 3 table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 10 v1.0, 2005-02 advance information p2.13 p2.14 p2.15 k14 f16 e16 i/o i o i i/o o i i/o o ? ? ? scl0 iic clock line 0 ccpos0_0 ccu60 hall input signal 0 slso1_3 ssc1 slave select output 3 ccpos0_1 ccu60 hall input signal 1 sda1 iic serial data line 1 slso0_4 ssc0 slave select output 4 ccpos0_2 ccu60 hall input signal 2 scl1 iic clock line 1 slso1_4 ssc1 slave select output 4 table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 11 v1.0, 2005-02 advance information p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 a15 b15 d15 e15 g14 g15 f15 h14 c15 h15 b16 i/o o o o i/o o o o i/o o o o i/o o o o i o o i o o o i i o o i o o puc puc puc puc puc puc puc puc puc puc puc port 3 port 3 is a 16-bit bi-direc tional general purpose i/o port which can be alternat ively used for mli1, ccu61, ssc0/1 and ocds le vel 2 debug lines. ocdsb_0 ocds l2 debug line b0 cout61_3 ccu61 compare channel 3 output ocdsb_1 ocds l2 debug line b1 cc61_0 ccu61 input/output of capture/ compare channel 0 ocdsb_2 ocds l2 debug line b2 cout61_0 ccu61 output of capture/compare channel 0 ocdsb_3 ocds l2 debug line b3 cc61_1 ccu61 input/output of capture/ co mpare channel 1 ocdsb_4 ocds l2 debug line b4 cout61_1 ccu61 output of capture/compare channel 1 ocdsb_5 ocds l2 debug line b5 cc61_2 ccu61 input/output of capture/ compare channel 2 ocdsb_6 ocds l2 debug line b6 cout61_2 ccu61 output of capture/compare channel 2 ocdsb_7 ocds l2 debug line b7 ctrap1 ccu61 trap input slso0_5 ssc0 slave select output 5 ocdsb_8 ocds l2 debug line b8 ccpos1_0 ccu61 hall input signal 0 tclk1 mli1 transmit channel clock output slso1_5 ssc1 slave select output 5 ocdsb_9 ocds l2 debug line b9 ccpos1_1 ccu61 hall input signal 1 tready1 mli1 transmit channel ready input slso0_6 ssc0 slave select output 6 ocdsb_10 ocds l2 debug line b10 ccpos1_2 ccu61 hall input signal 2 tvalid1 mli1 transmit channel valid output slso1_6 ssc1 slave select output 6 table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 12 v1.0, 2005-02 advance information p3.11 p3.12 p3.13 p3.14 p3.15 c16 d16 k13 j14 j15 o o o i o i o i o o i/o o i i/o o i i/o puc puc puc puc puc ocdsb_11 ocds l2 debug line b11 tdata1 mli1 transmit channel data output slso0_7 ssc0 slave select output 7 cc61_t12hr ccu61 timer 12 hardware run ocdsb_12 ocds l2 debug line b12 rclk1 mli1 receive channel clock input slso1_7 ssc1 slave select output 7 cc61_t13hr ccu61 timer 13 hardware run ocdsb_13 ocds l2 debug line b13 rready1 mli1 receive channel ready output mrst1b ssc1 master receive/slave transmit input/output b ocdsb_14 ocds l2 debug line b14 rvalid1 mli1 receive channel valid input mtsr1b ssc1 master transmit/slave receive input/output b ocdsb_15 ocds l2 debug line b15 rdata1 mli1 receive channel data input sclk1b ssc1 clock input/output line b p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 r8 r9 n7 n6 p6 r7 r6 p5 i/o o i o o i o i i o puc puc puc puc puc puc puc puc port 4 port 4 is an 8-bit bi-directi onal general purpose i/o port which can be alternat ively used for mli0 and scu. tclk0b mli0 transmit channel clock output b tready0b mli0 transmit channel ready input b tvalid0b mli0 transmit channel valid output b tdata0b mli0 transmit channel data output b rclk0b mli0 receive channel clock input b rready0b mli0 receive ch annel ready output b rvalid0b mli0 receive channel valid input b rdata0b mli0 receive ch annel data input b brkout _a ocds break out a table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 13 v1.0, 2005-02 advance information hdrst n5 i/o pua hardware reset input/re set indication output assertion of this bi-directi onal open-drain pin causes a synchronous reset of the chip through external circuitry. this pin must be driv en for a minimum 4 f cpu clock cycles. the internal reset ci rcuitry drives this pin in response to a power-on, hardware , watchdog and power-down wake-up reset for a specif ic period of time. for a software reset, activation of this pin is programmable. porst r5 i puc power-on reset input a low level on porst causes an asynchronous reset of the entire chip. porst is a fully asyn chronous level sensitive signal. nmi t7 i puc non-maskable interrupt input a high-to-low transition on this pi n causes an nmi-trap request to the cpu. trst t11 i pdc jtag module reset /enable input a low level at this pin rese ts and disables the jtag module. a high level enables the jtag module. tck t12 i puc jtag module clock input tdi t13 i puc jtag module serial data input tdo t10 o ? jtag module serial data output tms t9 i puc jtag module state ma chine control input trclk t8 o ? trace clock for ocds_l2 lines hwcfg0 hwcfg1 hwcfg2 m14 l14 t6 i i i puc puc pdc hardware configuration inputs the configuration i nputs define the b oot options of the TC1115 after a hardware invoked reset operation. brkin t5 i puc ocds break input a low level on this pin caus es a break in the chip?s execution when the ocds is enabled. in addition, the level of this pin during po wer-on reset determines the boot configuration. table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 14 v1.0, 2005-02 advance information cs0 cs1 cs2 cs3 d9 d8 c9 b8 o o o o puc puc puc puc ebu chip select output line 0 ebu chip select output line 1 ebu chip select output line 2 ebu chip select output line 3 each corresponds to a pr ogrammable region. only one can be active at one time. cscomb n3 o puc ebu chip select output for combination function (overlay memory and global) sdclki j1 i ? sdram clock inpu t (clock feedback) sdclko h1 o ? sdram clock output accesses to sdram devices are synchronized to this clock. ras d6 o puc ebu sdram row address strobe output cas d5 o puc ebu sdram column address strobe output cke l4 o puc ebu sdram clock enable output bfclki d1 i ? burst flash clock in put (clock feedback) bfclko e1 o ? burst flash clock output accesses to burst flash dev ices are synchronized to this clock. rd p2 o puc ebu read control line output in master mode input in slave mode rd/wr t3 o puc ebu write control line output in master mode input in slave mode wait b9 i puc ebu wait control line ale r3 o pdc ebu address latch enable output mr/w p3 o puc ebu motorola-style read/write output baa a11 o puc ebu burst addres s advance output for advancing address in a burst flash access adv b11 o puc ebu burst flash ad dress valid output table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 15 v1.0, 2005-02 advance information ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 c8 c7 b6 c6 c5 a3 a2 c3 c2 d2 f1 e3 f3 g1 h2 g3 d7 b5 a4 b4 c4 b3 b2 b1 c1 d3 e2 f2 f4 g4 h3 g2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc ebu address/data bu s input/output lines ebu address/data bus line 0 ebu address/data bus line 1 ebu address/data bus line 2 ebu address/data bus line 3 ebu address/data bus line 4 ebu address/data bus line 5 ebu address/data bus line 6 ebu address/data bus line 7 ebu address/data bus line 8 ebu address/data bus line 9 ebu address/data bus line 10 ebu address/data bus line 11 ebu address/data bus line 12 ebu address/data bus line 13 ebu address/data bus line 14 ebu address/data bus line 15 ebu address/data bus line 16 ebu address/data bus line 17 ebu address/data bus line 18 ebu address/data bus line 19 ebu address/data bus line 20 ebu address/data bus line 21 ebu address/data bus line 22 ebu address/data bus line 23 ebu address/data bus line 24 ebu address/data bus line 25 ebu address/data bus line 26 ebu address/data bus line 27 ebu address/data bus line 28 ebu address/data bus line 29 ebu address/data bus line 30 ebu address/data bus line 31 bc0 bc1 bc2 bc3 a5 a6 b7 a7 o o o o puc puc puc puc ebu byte control line 0 ebu byte control line 1 ebu byte control line 2 ebu byte control line 3 table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 16 v1.0, 2005-02 advance information a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 k1 l1 m1 n1 p1 j2 k2 l2 m2 n2 j3 k3 l3 m3 k4 a8 a9 a10 b10 c10 d10 t4 r4 p4 o o o o o o o o o o o o o o o o o o o o o o o o puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc puc ebu address bus input/output lines ebu address bus line 0 ebu address bus line 1 ebu address bus line 2 ebu address bus line 3 ebu address bus line 4 ebu address bus line 5 ebu address bus line 6 ebu address bus line 7 ebu address bus line 8 ebu address bus line 9 ebu address bus line 10 ebu address bus line 11 ebu address bus line 12 ebu address bus line 13 ebu address bus line 14 ebu address bus line 15 ebu address bus line 16 ebu address bus line 17 ebu address bus line 18 ebu address bus line 19 ebu address bus line 20 ebu address bus line 21 ebu address bus line 22 ebu address bus line 23 xtal1 xtal2 m16 n16 i o ? ? oscillator/pll/clock gener ator input/output pins xtal1 is the input to the ma in oscillator amplifier and input to the internal cloc k generator. xtal2 is the output of the main oscill ator amplifier circuit. for clocking of the device from an external source, xtal1 is driven with the clock si gnal while xtal2 is left unconnected. for crystal osc illator operation, xtal1 and xtal2 are co nnected to the cr ystal with the appropriate recommended oscillator circuitry. v ddosc3 p16 ?? main oscillator power supply (3.3 v) v ssosc3 r16 ?? main oscillator ground v ddosc l16 ?? main oscillator power supply (1.5 v) table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 general device information data sheet 17 v1.0, 2005-02 advance information note: p2.12 to p2.15 are always configured as open drain. v ssosc l15 ?? main oscillator ground v dd g7 g8 g9 g10 g13 k7,k8 k9 k10 ?? core and logic power supply (1.5 v) v ddp d4 d13 h4 j13 m4 n13 ?? ports power supply (3.3 v) v ss e4 e13 h7 h8 h9 h10 h13 j4,j7 j8,j9 j10 m13 n4 r2,t2 ?? ground n.c. a1 a16 t1,r1 t14 t15 t16 ?? not connected these pins must not be connected. 1) refers to internal pull-up or pull-down dev ice connected and corresponding type. the notation ? ? ? indicates that the internal pull-up or pull-down device is not enabled. table 2-1 pin definitions and functions (cont?d) symbol pin in out pu/ pd 1) functions
TC1115 functional description data sheet 18 v1.0, 2005-02 advance information 3 functional description 3.1 on-chip memories the TC1115 provides the following on- chip memories: ? program memory interface (pmi) with ? 32-kbyte scratch-pad code ram (spram) ? 16-kbyte instruction cache memory (icache) ? data memory interface (dmi) with ? 28-kbyte scratch-pad data ram (spram) ? 4-kbyte data cache memory (dcache) ? data memory unit (dmu) with ? 64-kbyte sram ? 16-kbyte boot rom (brom)
TC1115 functional description data sheet 19 v1.0, 2005-02 advance information 3.2 address map table 3-1 defines the specific segment oriented address blocks of the TC1115 with its address range, size, and pmi/dmi access view. table 3-2 shows the block address map of the segment 15 which in cludes on-chip peripheral un its and ports. table 3-1 TC1115 bl ock address map seg- ment address range size description dmi acc. pmi acc. 0 ? 7 0000 0000 h ? 7fff ffff h 2 gb mmu space via fpi via fpi c a c h e d 8 8000 0000 h ? 8fff ffff h 256 mb external memory space mapped from segment 10 via lmb via lmb 9 9000 0000 h ? 9fdf ffff h 256 mb reserved via fpi via fpi 10 a000 0000 h ? afbf ffff h 252 mb external memory space via lmb via lmb n o n- c a c h e d afc0 0000 h ? afc0 ffff h 64 kb dmu space afc1 0000 h ? afff ffff h ~4 mb reserved 11 b000 0000 h ? bfff ffff h 256 mb reserved via fpi via fpi 12 c000 0000 h ? c000 ffff h 64 kb dmu via lmb via lmb c a c h e d c001 0000 h ? cfff ffff h ~ 256 mb reserved
TC1115 functional description data sheet 20 v1.0, 2005-02 advance information 13 d000 0000 h ? d000 6fff h 28 kb dmi local data ram (ldram) dmi local via lmb non-cached d000 7000 h ? d3ff ffff h ~ 64 mb reserved d400 0000 h ? d400 7fff h 32 kb pmi local code scratch pad ram (spram) via lmb pmi local d400 8000 h ? d7ff ffff h ~64 mb reserved d800 0000 h ? ddff ffff h 96 mb external memory space via lmb via lmb de00 0000 h ? deff ffff h 16 mb emulator memory space df00 0000 h ? dfff bfff h ~16 mb reserved ? ? dfff c000 h ? dfff ffff h 16 kb boot rom space via fpi via fpi 14 e000 0000 h ? e7ff ffff h 128 mb external memory space via lmb via lmb e800 0000 h ? e83f ffff h 4 mb reserved for mapped space for lower 4 mbytes of local memory in segment 12 (transformed by lfi bridge to c000 0000 h ? c03f ffff h ) access only from fpi bus side of lfi access only from fpi bus side of lfi e840 0000 h ? e84f ffff h 1 mb reserved for mapped space for lower 1 mbyte of local memory in segment 13 (transformed by lfi bridge to d000 0000 h ? d00f ffff h ) access only from fpi bus side of lfi access only from fpi bus side of lfi e850 0000 h ? e85f ffff h 1 mb reserved for mapped space for 1 mbyte of local memory in segment 13 (transformed by lfi bridge to d400 0000 h ? d40f ffff h ) table 3-1 TC1115 bl ock address map (cont?d) seg- ment address range size description dmi acc. pmi acc.
TC1115 functional description data sheet 21 v1.0, 2005-02 advance information 14 e860 0000 h ? efff ffff h 122 mb reserved ? ? n o n- c a c h e d 15 f000 0000 h - ffff ffff h 256 mb see table 3-2 via lmb or via fpi via lmb or via fpi table 3-2 block addre ss map of segment 15 symbol description address range size system peripheral bus (spb) scu system control unit (incl. wdt) f000 0000 h - f000 00ff h 256 bytes sbcu fpi bus control unit f000 0100 h - f000 01ff h 256 bytes stm system timer f000 0200 h - f000 02ff h 256 bytes ocds on-chip debug support (cerberus) f000 0300 h - f000 03ff h 256 bytes ? reserved f000 0400 h - f000 04ff h 256 bytes ? reserved f000 0500 h - f000 05ff h 256 bytes gptu general purpose timer unit f000 0600 h - f000 06ff h 256 bytes ? reserved f000 0700 h - f000 07ff h 256 bytes ? reserved f000 0800 h - f000 08ff h 256 bytes ? reserved f000 0900 h - f000 09ff h 256 bytes ? reserved f000 0a00 h - f000 0aff h 256 bytes ? reserved f000 0b00 h - f000 0bff h 256 bytes p0 port 0 f000 0c00 h - f000 0cff h 256 bytes p1 port 1 f000 0d00 h - f000 0dff h 256 bytes p2 port 2 f000 0e00 h - f000 0eff h 256 bytes p3 port 3 f000 0f00 h - f000 0fff h 256 bytes p4 port 4 f000 1000 h - f000 10ff h 256 bytes ? reserved f000 1100 h - f000 11ff h 256 bytes table 3-1 TC1115 bl ock address map (cont?d) seg- ment address range size description dmi acc. pmi acc.
TC1115 functional description data sheet 22 v1.0, 2005-02 advance information ? reserved f000 1200 h - f000 12ff h 256 bytes ? reserved f000 1300 h - f000 13ff h 256 bytes ? reserved f000 1400 h - f000 14ff h 256 bytes ? reserved f000 1500 h - f000 15ff h 256 bytes ? reserved f000 1600 h - f000 16ff h 256 bytes ? reserved f000 1700 h - f000 17ff h 256 bytes ? reserved f000 1800 h - f000 18ff h 256 bytes ? reserved f000 1900 h - f000 19ff h 256 bytes ccu60 capture/compare unit 0 f000 2000 h - f000 20ff h 256 bytes ccu61 capture/compare unit 1 f000 2100 h - f000 21ff h 256 bytes ? reserved f000 2200 h - f000 3bff h ? dma direct memory access controller f000 3c00 h - f000 3eff h 3 256 bytes ? reserved f000 3f00 h - f000 3fff h ? can multican controller f000 4000 h - f000 5fff h 8 kbytes ? reserved f000 6000 h - f00e 1fff h ? ? reserved; these locations should not be written. f00e 2000 h - f00e 219f h 416 bytes ? reserved; these locations should not be written. f00e 21a0 h - f00e 27ff h 1.6 kbytes ? reserved; these locations should not be written. f00e 2800 h - f00e 28ff h 256 bytes ? reserved f00e 2900 h - f00f ffff h ? units on smif interf ace of dma controller ? reserved f010 0000 h - f010 00ff h 256 bytes ssc0 synchronous serial interface 0 f010 0100 h - f010 01ff h 256 bytes ssc1 synchronous serial interface 1 f010 0200 h - f010 02ff h 256 bytes asc0 async./sync. serial interface 0 f010 0300 h - f010 03ff h 256 bytes asc1 async./sync. serial interface 1 f010 0400 h - f010 04ff h 256 bytes asc2 async./sync. serial interface 2 f010 0500 h - f010 05ff h 256 bytes i2c inter ic f010 0600 h - f010 06ff h 256 bytes table 3-2 block addre ss map of segment 15 (cont?d) symbol description address range size
TC1115 functional description data sheet 23 v1.0, 2005-02 advance information ? reserved f010 0700 h - f010 bfff h ? mli0 micro link interface 0 f010 c000 h - f010 c0ff h 256 bytes mli1 micro link interface 1 f010 c100 h - f010 c1ff h 256 bytes mchk memory checker f010 c200 h - f010 c2ff h 256 bytes ? reserved f010 c300 h - f01d ffff h ? mli0_ sp0 mli0 small transfer window 0 f01e 0000 h - f01e 1fff h 8 kbytes mli0_ sp1 mli0 small transfer window 1 f01e 2000 h - f01e 3fff h 8 kbytes mli0_ sp2 mli0 small transfer window 2 f01e 4000 h - f01e 5fff h 8 kbytes mli0_ sp3 mli0 small transfer window 3 f01e 6000 h - f01e 7fff h 8 kbytes mli1_ sp0 mli1 small transfer window 0 f01e 8000 h - f01e 9fff h 8 kbytes mli1_ sp1 mli1 small transfer window 1 f01e a000 h - f01e bfff h 8 kbytes mli1_ sp2 mli1 small transfer window 2 f01e c000 h - f01e dfff h 8 kbytes mli1_ sp3 mli1 small transfer window 3 f01e e000 h - f01e ffff h 8 kbytes ? reserved f01f 0000 h - f01f ffff h ? mli0_ lp0 mli0 large transfer window 0 f020 0000 h - f020 ffff h 64 kbytes mli0_ lp1 mli0 large transfer window 1 f021 0000 h - f021 ffff h 64 kbytes mli0_ lp2 mli0 large transfer window 2 f022 0000 h - f022 ffff h 64 kbytes mli0_ lp3 mli0 large transfer window 3 f023 0000 h - f023 ffff h 64 kbytes mli1_ lp0 mli1 large transfer window 0 f024 0000 h - f024 ffff h 64 kbytes mli1_ lp1 mli1 large transfer window 1 f025 0000 h - f025 ffff h 64 kbytes table 3-2 block addre ss map of segment 15 (cont?d) symbol description address range size
TC1115 functional description data sheet 24 v1.0, 2005-02 advance information mli1_ lp2 mli1 large transfer window 2 f026 0000 h - f026 ffff h 64 kbytes mli1_ lp3 mli1 large transfer window 3 f027 0000 h - f027 ffff h 64 kbytes ? reserved f028 0000 h - f200 00ff h ? ? reserved; these locations should not be written. f200 0100 h - f200 05ff h 1280bytes ? reserved f200 0600 h - f7e0 feff h ? cpu (part of system peripheral bus) cpu sfrs cpu slave interface f7e0 ff00 h -f7e0 ffff h 256 bytes reserved f7e1 0000 h - f7e1 7fff h ? mmu f7e1 8000 h - f7e1 80ff h 256 bytes reserved f7e1 8100 h - f7e1 bfff h ? memory protection registers f7e1 c000 h - f7e1 efff h 12 kbytes reserved f7e1 f000 h - f7e1 fcff h ? core debug register (ocds) f7e1 fd00 h - f7e1 fdff h 256 bytes core special f unction registers (csfrs) f7e1 fe00 h - f7e1 feff h 256 bytes general purpose register (gprs) f7e1 ff00 h - f7e1 ffff h 256 bytes ? reserved f7e2 0000 h - f7ff ffff h ? local memory buses (lmb) ebu external bus inte rface unit f800 0000 h - f800 03ff h 1 kbyte dmu data memory unit f800 0400 h - f800 04ff h 256 bytes ? reserved f800 0500 h - f87f fbff h ? dmi data memory interface unit f87f fc00 h - f87f fcff h 256 bytes pmi program memory interface unit f87f fd00 h - f87f fdff h 256 bytes lbcu local memory bus control unit f87f fe00 h - f87f feff h 256 bytes lfi lmb to fpi bu s bridge f87f ff00 h - f87f ffff h 256 bytes ? reserved f880 0000 h - ffff ffff h ? table 3-2 block addre ss map of segment 15 (cont?d) symbol description address range size
TC1115 functional description data sheet 25 v1.0, 2005-02 advance information 3.3 memory protection system the TC1115 memory protection system spec ifies the addressable range and read/write permissions of memory segmen ts available to the currently executing task. the memory protection system cont rols the position and range of addressable segments in memory. it also controls the types of read and write operations allowed within addressable memory segments. any illegal memory access is detected by the memo ry protection hardware, which then invokes the appropriate trap service routine (tsr) to handle the error. thus, the memory protection system pr otects critical system functions against both software and hardware erro rs. the memory protection hardware can also generate signals to the debu g unit to facilitate tracing illegal memory accesses. in TC1115, tricore? supports two address spaces: the virtual ad dress space and the physical address space. both address sp ace are 4 gbytes in si ze and divided into 16 segments with each segment being 256 m bytes. the upper 4 bits of the 32-bit address are used to identify the segment. virtual segments are number ed 0 - 15. but a virtual address is always translated into a physical address bef ore accessing memory. the virtual address is translated into a physical addre ss using one of two translation mechanisms: (a) direct transl ation, and (b) page table entry (pte) based translation. if the virtual address be longs to the upper half of the virtual address space then the virtual address is directly used as the physical address (direct translati on). if the virtual address belongs to the lower half of the address space, then the vi rtual address is used directly as the physical address if the processor is operating in physical mo de (direct translation) or translated using a page tabl e entry if the processor is op erating in virtual mode (pte translation). these are managed by memory managem ent unit (mmu). memory protection is enforced using separate me chanisms for the tw o translation paths. 3.3.1 protection for direct translation memory protection for addresse s that undergo direct translat ion is enforced using the range based protection that has been used in the previous generation of the tricore? architecture. the range bas ed protection mechanism prov ides support for protecting memory ranges from unauthor ized read, write, or inst ruction fetch accesses. the tricore? architecture provides up to four protection register se ts with the psw.prs field controlling the selection of the protection register se t. because the TC1115 uses a harvard-style memory architec ture, each memory protecti on register set is broken down into a data protection register set an d a code protection re gister set. each data protection register set can sp ecify up to four address ranges to rece ive particular protection modes. each code protection re gister set can specif y up to two address ranges to receive particular protection modes. each of the data protecti on register sets and code protection register sets determines the range and prot ection modes for a separate memory area. each contains register pairs which determine the addre ss range (the data segment protection registers and code segment pr otection registers) and o ne register (data protection
TC1115 functional description data sheet 26 v1.0, 2005-02 advance information mode register) which determines the me mory access modes which apply to the specified range. 3.3.2 protection for pte based translation memory protection for addres ses that undergo pte based tr anslation is enforced using the pte used for the address translation. the pte pr ovides support for protecting a process from unauthoriz ed read, write, or instruction fetches by other processes. the pte has the following bits that are pr ovided for the purpose of protection: ? execute enable (xe) enables instructio n fetch to the page ? write enable (we) enables data wr ites to the page ? read enable (re) enables data reads from the page furthermore, user-0 accesses to virtual addresses in th e upper half of the virtual address space are disallowed when operating in virtual mo de. in physical mode, user-0 accesses are disallowed only to segments 14 and 15. any user-0 access to a virtual address that is restricted to user-1 or supervisor mode will cause a virtual address protection (vap) trap in both the physical and virtual modes. 3.3.3 memory checker the memory checker mo dule (mchk) makes it possible to check th e data consistency of memories. it uses dma moves to read from the selected a ddress area and to write the value read in a memory checke r input register (the moves should be 32-b it moves). a polynomial checksum calculation is done wi th each write oper ation to the memory checker input register.
TC1115 functional description data sheet 27 v1.0, 2005-02 advance information 3.4 on-chip bus system the TC1115 includes two bus systems: ? local memory bus (lmb) ? flexible peripheral interface bus (fpi) the lmb-to-fpi (lfi) bridge inte rconnects the fpi bus and lmb bus. 3.4.1 local memory bus (lmb) the local memory bus interc onnects the memory units a nd functional units, such as cpu and dmu. the main obje ctive of the lmb bus is to support devices with fast response time. this al lows the dmi and pmi fast access to loca l memory and reduces load on the fpi bus. the tr icore? system itself is loca ted on the lmb the bus. via external bus unit, it interconnects TC1115 an d external components. the local memory bus is a syn chronous, pipelined, split bus with va riable block size transfer support. it supports 8, 16, 32 and 64 bits single beat transa ctions and variable length 64 bits block transfers. features: the lmb provides the following features: ? synchronous, pipelined, multimas ter, 64-bit high performance bus ? optimized for high s peed and high performance ? 32-bit address, 64-bit data buses ? central, simple per cycle arbitration ? slave controlled wa it state insertion ? address pipelining (max depth - 2) ? supports spli t transactions ? supports variable bl ock size transfer ? supports locked transact ion (read-modify-write) 3.4.2 flexible peripheral interconnect bus (fpi) the fpi bus is an on-chip bus that is used in modular and highly integrated microprocessors and microcontrollers ( systems-on-chips ). fpi bus is designed for memory mapped data transfers between its bus agents. bus agents are on-chip function blocks (modules), equipped with an fp i bus interface and c onnected via fpi bus signals. an fpi bus ag ent acts as an fpi bu s master when it initiates data read or data write operations once bus ownership has been granted to the a gent. an fpi bus agent that is addressed by an fpi bus operation acts as an fp i bus slave when it performs the requested data read or write operation.
TC1115 functional description data sheet 28 v1.0, 2005-02 advance information features: the fpi bus is designed with the requirements of high-p erformance systems in mind. the features are: ? core independent ? multimaster capabilit y (up to 16 masters) ? demultiplexed operation ? clock synchronous ? peak transfer rate of up to 80 0 mbytes/sec (@ 100 mhz bus clock) ? address and data bus scalable (address bu s up to 32 bits, data bus up to 64 bits) ? 8-/16-/32- and 64-bit data transfers ? broad range of transfer types from single to multiple data transfers ? split transaction su pport for agents with long response time ? burst transfer capability ? emi and power consumption minimized 3.4.3 lfi the lmb-to-fpi interface (lfi) block provides the ci rcuitry to interfac e (bridge) the fpi bus and the local memory bus (lmb). lfi features: ? full support for bus transactions found wi thin current tricore? 1.3 based systems: ? single 8/16/32-bit write/read transfers from fpi to lmb ? single 8/16/32/64-bit write/re ad transfers from lmb to fpi ? read-modify-write transfers of 8/16/32-bit in both directions ? burst transactions of 2, 4 or 8 data beats from t he fpi to the lmb ? burst transactions of 2 or 4 da ta beats from the lmb to the fpi ? address decoding a nd translation as required by tricore? 1.3 implementation ? fpi master interf ace supports full pi pelining on fpi bus ? lmb master interface suppo rts pipelining on lmb with in the scope of the lmb specification ? fpi master interface can act as default master on fpi bus ? programmable support for split lmb to fpi read transactions ? retry generation on both fpi and lmb buses ? full support for abort, retry, error and fpi timeout conditions ? flexible lmb/fpi clock rati o support including dynami c clock switching support ? lfi core clock may be shut down when no transactions ar e being issued to lfi from either bus and the lfi ha s no transactions in prog ress, thus saving power.
TC1115 functional description data sheet 29 v1.0, 2005-02 advance information 3.5 lmb external bus unit the lmb external bus control unit (ebu) of the TC1115 is the interface between external resources, like memories and per ipheral units, and th e internal resources connected to on-chip bus es if enabled. the ba sic structure and exte rnal interconnections of the ebu are shown in figure 3-1 . figure 3-1 ebu structure and interface mcb04941_mod ebu_lmb ad[31:0] bc[3:0] a[23:0] rd rd/wr wait cscomb adv ale ras cs[3:0] bfclko cas cke mr/w p1.15/rmw p0.5/hold bfclki baa 32 4 24 4 lmb pmi dmi lfi mmu tri core tm fpi to peripherals sdclki sdclko port 0 control p0.6/hlda p0.4/breq port 1 control p2.0/csemu port 2 control
TC1115 functional description data sheet 30 v1.0, 2005-02 advance information the ebu is used primarily fo r any local memory bus (lmb ) master accessing external memories. the ebu controls all transactions required for this operation and in particular handles the arbitration betwe en the internal ebu master and the external ebu master. the types of external devices/bus modes cont rolled by the ebu are: ? intel-style perip herals (separate rd and wr signals) ?roms, eproms ?static rams ? pc100 and pc133 sdrams (burst read/w rite capacity/multi -bank/page support) ? specific types of burs t mode flash devices ? special support for extern al emulator/debug hardware features: ? supports 64-bit local memory bus (lmb) ? supports external bus frequency: internal lmb frequency = 1:1 or 1:2 ? provides highly programm able access parameters ? supports intel-style peripherals/devices ? supports pc100 and pc133 (runs in maximum 120 mhz ) sdram (burst access, multibanking, precharge, refresh) ? supports 16- and 32-bit sdram data bus and 64-,12 8-, and 256-mbit devices ? supports burst flash devices ? supports multiplexed access (address and data on the same bus) when pc100 and pc133 sdram are not presen ted on the external bus ? supports data buffering : code prefetch buffe r, read/write buffer ? external master arbitration compatible to c166 and other tricore? devices ? provides 4 programmable address regions (1 ded icated for emulator) ? provides a csglb signal, bit programmable to combine one or more cs lines for buffer control ? provides rmw signal reflecting re ad-modify-write action ? supports little en dian byte ordering ? provides signal for controlling data flow of sl ow-memory buffer
TC1115 functional description data sheet 31 v1.0, 2005-02 advance information 3.6 direct memory access (dma) the direct memory access controller executes dma tr ansactions from a source address location to a destin ation address location, without intervention of the cpu. one dma transaction is controlled by one dm a channel. each dma channel has assigned its own channel register set. the total of 8 channe ls are provided by one dma sub-block. the dma module is co nnected to 3 bus inte rfaces in TC1115, the flexible peripheral interconnect bus (fpi), the dma bus and the mi cro link bus. it c an do transfers on each of the buses as well as between the buses. in addition, it bridge s accesses from the fl exible peripheral inte rconnect bus to the peripherals on the dma bus, al lowing easy access to thes e peripherals by cpu. clock control, address decoding, dma request wiring, and dm a interrupt service request control are implementation specific and managed outside the dma controller kernel. features: ? 8 independent dma channels ? up to 8 selectable reques t inputs per dma channel ? programmable priority of dma channels with in a dma sub-block (2 levels) ? software and hardware dma request generation ? hardware requests by selected peripherals and exter nal inputs ? programmable priority of the dm a sub-block on the bus interfaces ? buffer capability for move actions on th e buses (min. 1 move per bus is buffered). ? individually programma ble operation modes fo r each dma channel ? single mode: stops and disables dma chan nel after a predefined number of dma transfers ? continuous mode: dma chann el remains enabled after a predefined number of dma transfers; dma transaction can be repeated. ? programmable address modification ? full 32-bit addressi ng capability of each dma channel ? 4-gbyte address range ? support of circular buffer addressing mode ? programmable data width of a dma tr ansaction: 8-bit, 16-bit, or 32-bit ? micro link supported ? register set for each dma channel ? source and destinatio n address register ? channel control an d status register ? transfer count register ? flexible interrupt generation (the service req uest node logic for the mli channels is also implemented in the dma module) ? all buses/interfaces connec ted to the dma module must work at the same frequency. ? read/write requests of the fp i bus side to the remote pe ripherals are bridged to the dma bus (only the dma is master on the dma bus)
TC1115 functional description data sheet 32 v1.0, 2005-02 advance information the basic structure and ex ternal interconnections of the dma are shown in figure 3-2 . figure 3-2 dma controller stru cture and interconnections dma request wi ri ng matri x interrupt control TC1115_dmaimplementation cl ock control address decoder dma controller arbiter/ switch control switch bus interface 0 m/s bus interface 2 smif sr [3:0] f dma asc0 2 2 asc1 2 2 asc2 ssc0 2 1 ssc1 4 ccu60 4 4 scu (ext.trg) mli1 dma interrupt control unit 4 multican to fpi bus mli0 1 i2c ccu61 4 sr [15:12] 1 channel 00-07 registers dma sub-block 0 request assignment and priorisation uni t 0 8 transaction control engine 8 bus interface 1 m/s asc0 asc1 asc2 ssc0 ssc1 iic dma bus mli0 mli1 mem check dma bus
TC1115 functional description data sheet 33 v1.0, 2005-02 advance information 3.7 interrupt system an interrupt request can be serviced by the cpu, which is called ?service provider?. interrupt requests are refe rred to as ?service requ ests? in this document. each peripheral in the tc1 115 can generate service requ ests. additiona lly, the bus control unit, the debug unit, the dma controller and even the cpu itself can generate service requests to the service provider. as shown in figure 3-3 , each unit that can generate service requ ests is connected to one or multiple se rvice request nodes (srn). each srn contains a service requ est control register mod_src, where ?mod? is the identifier of the unit requesting service. the srns are conne cted to the interrupt control unit (icu) via the cp u interrupt arbitration bus. the icu arbitrates service requests for the cpu and administer s the interrupt arbitration bus. units that can generat e service requests are: ? asynchronous/synchronous se rial interfaces (asc0, asc1 and asc2) with 4 srns each ? high-speed synchro nous serial interfaces (ssc0 and ssc1) with 3 srns each ? inter ic interface (iic) with 3 srns ? micro link interface mli0 with 4 srns and ml i1 with 2 srns ? general purpose timer unit (gptu) with 8 srns ? capture/compare un it (ccu60 and ccu61) with 4 srns each ? multican (can) with 16 srns ? external interrupts with 4 srns ? direct memory access cont roller (dma) with 4 srns ? dma bus with 1 srn ? system timer (stm) with 2 srns ? bus control units (sbcu and lbcu) with 1 srn each ? central processing unit (cpu) with 4 srns ? floating point unit (fpu) with 1 srn ? debug unit (ocds) with 1 srn the cpu can make service requ ests directly to itself (v ia the icu). the cpu service request nodes are acti vated through software.
TC1115 functional description data sheet 34 v1.0, 2005-02 advance information figure 3-3 block diagram of the TC1115 interrupt system service req. nodes service req. nodes service requestors interruptsys_cedar_TC1115 cpu interrupt arbitration bus service requestors 4 srns 4 asc0 4 4 srns 4 asc1 4 4 srns 4 asc2 4 3 srns 3 ssc0 3 4 srns 4 mli0 4 3 srns 3 ssc1 3 2 srns 2 mli1 2 16 srns 16 multican 16 4 srns dma 4 4 1 srn sbcu 1 1 1 srn lbcu 1 1 4 srns ccu61 4 4 4 srns ccu60 4 4 4 srn ext. int. 4 4 3 srns iic 3 3 service req. nodes 4 4 srns 4 cpu interrupt control unit interrupt service providers int. req. pipn cpu ccpn int. ack. software interrupts icu 8 srns 8 gptu 8 2 srns 2 stm 2 1 srn 1 fpu 1 1 srn 1 ocds 1 1 srn 1 dma bus 1
TC1115 functional description data sheet 35 v1.0, 2005-02 advance information 3.8 parallel ports the TC1115 has 72 digi tal input/output port lines, which ar e organized into four parallel 16-bit ports and one parallel 8-bit port, port p0 to port p4 with 3.3 v nominal voltage. the digital parallel po rts can be used as general purpos e i/o lines or th ey can perform input/output functions for the on-chip peripheral units. an overview on the port-to- peripheral unit assignment is shown in figure 3-4 . figure 3-4 parallel ports of the TC1115 mc a 0 4 9 5 1 mo d TC1115 paral l el ports gpio3 gpio4 gpio al ternate functi ons ssc0/ ssc1/ ccu61/ mli1/ ocds mli0/ scu gpio1 gpio0 gpio2 gpio al ternate functi ons asc0/ asc1/ asc2/ ssc0/ ssc1/ iic/ ccu60/ ebu/ scu ssc0/ ssc1/ mul ti can/ ebu/ scu/ ocds gptu/ asc1/ asc2/ ssc0/ ssc1/ ccu60/ mul ti can/ mli0/ ebu/ scu/ external interrupts 16 16 16 8 16
TC1115 functional description data sheet 36 v1.0, 2005-02 advance information 3.9 asynchronous/synchronous serial interface (asc) figure 3-5 shows a global view of the func tional blocks of three asynchronous/ synchronous serial interfaces (asc0, asc1 and asc2). each asc module (asc0/asc1/asc2) communica tes with the extern al world via one pair of i/o lines. the rxd line is the receiv e data input signal (i n synchronous mode also output). txd is the transmit output signal. clock control, address decoding, and interrupt service request control are manage d outside the asc module kernel. the asynchronous/synchrono us serial interfaces pr ovide serial communication between the TC1115 and other microcontr ollers, microprocessors or external peripherals. each asc supports full-d uplex asynchronous commu nication and half-duplex synchronous communication. in synchronous mode, data is transmitted or received synchronous to a shift clock which is generat ed by the asc intern ally. in asynchronous mode, 8-bit or 9-bit data transfer, parity g eneration, and th e number of stop bits can be selected. parity, framing, and overrun erro r detection are provi ded to increase the reliability of data transfers. transmission and reception of data is double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back opti on. a 13-bit baud-rate generator provides the asc with a separa te serial clock signal that can be accurately adjusted by a prescaler implemented as a fractional divider.
TC1115 functional description data sheet 37 v1.0, 2005-02 advance information figure 3-5 general block diag ram of the asc interfaces mcb04485_mod asc0 module (kernel) port control asc1 module (kernel) clock control address decoder interrupt control f asc1 to dma eir tbir tir rir clock control address decoder interrupt control f asc0 to dma eir tbir tir rir p2.0/ rxd0 p2.1/ txd0 p0.0/ rxd1b p0.1/ txd1b p2.8/ rxd1a p2.9/ txd1a rxd_i1 rxd_o rxd_i0 txd_o rxd_i1 rxd_o rxd_i0 txd_o asc2 module (kernel) clock control address decoder interrupt control f asc1 to dma eir tbir tir rir p0.2/ rxd2b p0.3/ txd2b p2.10/ rxd2a p2.11/ txd2a rxd_i1 rxd_o rxd_i0 txd_o
TC1115 functional description data sheet 38 v1.0, 2005-02 advance information features: ? full-duplex asynchrono us operating modes ? 8-bit or 9-bit data frames, lsb first ? parity bit generation/checking ? one or two stop bits ? baud rate from 4.6875 mbaud to 1.1 baud (@ 75 mhz clock) ? multiprocessor mode for automatic address/ data byte detection ? loop-back capability ? half-duplex 8-bit syn chronous operating mode ? baud rate from 9.375 mbaud to 762.9 baud (@ 75 mhz clock) ? support for irda data transmis sion up to 115.2 kbaud maximum ? double buffered transmitter/receiver ? interrupt generation ? on a transmitter bu ffer empty condition ? on a transmit last bit of a frame condition ? on a receiver buff er full condition ? on an error condit ion (frame, parity , overrun error) ?fifo ? 8-byte receive fifo (rxfifo) ? 8-byte transmit fifo (txfifo) ? independent control of rxfifo and txfifo ? 9-bit fifo data width ? programmable receive/trans mit interrupt trigger level ? receive and transmit fifo filling level indication ? overrun error generation ? underflow error generation
TC1115 functional description data sheet 39 v1.0, 2005-02 advance information 3.10 high-speed synchronous serial interface (ssc) figure 3-6 shows a global view of the functional blocks of two high-speed synchronous serial interfaces (ssc0 and ssc1). each ssc supports fu ll-duplex and ha lf-duplex serial synchro nous communication up to 37.5 mbaud (@ 75 mhz module clock) with re ceive and transmit fifo support. the serial clock signal can be generated by the ssc itself (master mode) or can be received from an external master (slave mode). data width, shift directio n, clock polarity and phase are programmable. thi s allows communication wi th spi-compatible devices. transmission and reception of data is double -buffered. a shift cl ock generator provides the ssc with a separate serial clock signal. eight slave sele ct inputs are available for slave mode operation. eight programmable slave select ou tputs (chip selects) are supported in master mode. features: ? master and slav e mode operation ? full-duplex or half-duplex operation ? automatic pad control possible ? flexible data format ? programmable number of data bits: 2 to 16 bits ? programmable shift directi on: lsb or msb shift first ? programmable clock polarity: idle lo w or high state fo r the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock ? baud rate generation minimum at 572.2 baud (@ 75 mh z module clock) ? interrupt generation ? on a transmitte r empty condition ? on a receiver full condition ? on an error condit ion (receive, phase, bau d rate, transmit error) ? four-pin interface ? flexible ssc pin configuration ? up to eight slave select inputs in slave mode ? up to eight programmable slave sele ct outputs slso in master mode ? automatic slso generation with programmable timing ? programmable active le vel and enable control ? 4-stage receive fifo (rxfifo) an d 4-stage transmit fifo (txfifo) ? independent control of rxfifo and txfifo ? 2- to 16-bit fifo data width ? programmable receive/transmi t interrupt trigger level ? receive and transmit fifo filling level indication ? overrun error generation ? underflow error generation
TC1115 functional description data sheet 40 v1.0, 2005-02 advance information figure 3-6 general block diag ram of the ssc interfaces port 1 control mcb04486_mod cl oc k control address decoder interrupt control f ssc0 address decoder interrupt control to dma eir tir rir to dma eir tir rir port 2 control ssc0 module (kernel ) mrstb mtsr master slsi1 slso[2:1] mrsta mtsrb mrst mtsra sclkb slck sclka slave slave master slave master port 2 control ssc1 module (kernel ) mrstb mtsr master slso[7:5] mrsta mtsrb mrst mtsra sclkb slck sclka slave slave master master p2.3/mtsr0 p2.2/mrst0 p2.4/sclk0 p2.5/mrst1a p1.15/slsi0 f cl c0 f ssc1 f cl c1 cl ock control slsi[7:2] 1) slsi1 slave slsi[7:2] 1) enable m/s sel ect p1.11/slso01 1) these lines are not connected slso0 enable 1) m/s sel ect 1) 1) 1) p1.13/slso02 p2.12/slso03 p2.14/slso04 slso[4:3] port 0 control p0.6/slso00 p0.7/slso10 port 3 control slso[7:5] p3.7/slso05 p3.9/slso06 p3.11/slso07 p3.8/slso15 p3.10/slso16 p3.12/slso17 slso0 slso[2:1] slso[4:3] port 1 control p1.12/slso11 p1.14/slso12 p3.13/mrst1b p2.6/mtsr1a p3.14/mtsr1b p2.7sclk1a p3.15/sclk1b p2.13/slso13 p2.15/slso14 p0.4/slsi1
TC1115 functional description data sheet 41 v1.0, 2005-02 advance information 3.11 inter ic serial interface (iic) figure 3-7 shows a global view of th e functional blocks of the inter ic serial interface (iic). the iic module has four i/o li nes, located at port 2. the iic module is further supplied with clock control, interrupt control and address deco ding logic. one dma request can be generated by iic module. figure 3-7 general block diagram of the iic interface the on-chip iic bus module conn ects the platform buses to other external controllers and/or peripherals via the two-line serial ii c interface. one line is responsible for clock transfer and synchronization (s cl), the other is responsible for the data transfer (sda). the iic bus module provides communication at data rates of up to 400 kbit/sec and features 7-bit addressing as we ll as 10-bit addres sing. this module is fully compatible to the iic bus protocol. the module can operate in three different modes: master mode , where the iic controls the bus transa ctions and provides the clock signal. slave mode , where an external master controls the bus transactions and provides the clock signal. multimaster mode , where several masters can be connec ted to the bus, i.e. the iic can be master or slave. the on-chip iic bus mo dule allows efficient communicati on via the common iic bus. the module unloads the cpu of low level tasks such as: ? (de)serialization of bus data ? generation of star t and stop conditions ? monitoring the bus lines in slave mode address decoder interrupt control iic module port 2 control p2.13/scl0 p2.15/scl1 sda0 p2.14/sda1 p2.12/sda0 clock control f iic scl0 sda1 scl1 int_p int_e int_d to dma
TC1115 functional description data sheet 42 v1.0, 2005-02 advance information ? evaluation of the devic e address in slave mode ? bus access arbitratio n in multimaster mode features: ? extended buffer allows up to 4 send/receive data bytes to be stored ? selectable baud rate generation ? support of standard 100 kbaud and extended 400 kbaud data rates ? operation in 7-bit a ddressing mode or 10-b it addressing mode ? flexible control via interrupt se rvice routines or by polling ? dynamic access to up to 2 physical iic buses
TC1115 functional description data sheet 43 v1.0, 2005-02 advance information 3.12 multican figure 3-8 shows a global view of the functional blocks of the multican module. figure 3-8 general block diagram of the multican interface the multican module cont ains 4 full-can nodes op erating independently or exchanging data and remo te frames via a gateway functi on. transmission and reception of can frames is handled in ac cordance to can specificatio n v2.0 b (active). each can node can receive and tran smit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. all can nodes share a common set of message objects, where each message object may be individually allocate d to one of the can nodes. besides serving as a storage container for incoming and outgoing frames, message objects may be combined to build gateways between the can node s or to setup a fifo buffer. the message objects are orga nized in double chai ned lists, where each can node has its own list of message object s. a can node stores frames only into message objects that are allocated to the list of the can node. it only transm its messages from objects of this list. a powerful, command driv en list controller performs all list operations. mul ti can modul e kernel interrupt control f can port 0 control can node 1 can control message object buffer 128 objects txdc0a rxdc0a can node 0 can node 2 can node 3 txdc1a rxdc1a txdc2 rxdc2 txdc3 rxdc3 linked list control p0.15 / txdcan3 p0.14 / rxdcan3 p0.13 / txdcan2 p0.12 / rxdcan2 p0.11 / txdcan1a p0.10 / rxdcan1a p0.9 / txdcan0a p0.8 / rxdcan0a f cl c cl ock control address decoder dma int_o [3:0] int_o [15:4] int_o15 port 1 control p1.1 / txdcan0b p1.0 / rxdcan0b p1.3 / txdcan1b p1.2 / rxdcan1b txdc1b rxdc1b txdc0b rxdc0b
TC1115 functional description data sheet 44 v1.0, 2005-02 advance information the bit timings for the ca n nodes are derived from the peripheral clock ( f can ) and are programmable up to a data ra te of 1 mbaud. a pair of rece ive and transmit pins connects each can node to a bus transceiver. features: ? compliant to iso 11898 ? can functionality according to can specification v2.0 b (active) ? dedicated control registers ar e provided for each can node ? a data transfer rate up to 1 mbaud is supported ? flexible and powerful message transfer control and erro r handling cap abilities are implemented ? advanced can bus bit timing analysis and baud rate detection can be performed for each can node vi a the frame counter ? full-can functionality: a set of 12 8 message objects can be individually ? allocated (assigned ) to any can node ? configured as transmi t or receive object ? setup to handle fr ames with 11-bit or 29-bit identifier ? counted or assi gned a timestamp vi a a frame counter ? configured to remote monitoring mode ? advanced acceptance filtering: ? each message object provides an indivi dual acceptance mask to filter incoming frames. ? a message object c an be configured to accept only standard or only extended frames or to accept both standard and extended frames. ? message objects c an be grouped into 4 priority classes. ? the selection of the message to be tran smitted first c an be performed on the basis of frame identifier, ide bit and rtr bi t according to can arbitration rules. ? advanced message ob ject functionality: ? message objects can be combined to build fifo message buffers of arbitrary size, which is only limited by the to tal number of message objects. ? message objects can be link ed to form a gateway to au tomatically transfer frames between two different can bu ses. a single gateway c an link any two can nodes. an arbitrary number of gateways may be defined. ? advanced data management: ? the message objects are organi zed in double chained lists. ? list reorganizations may be performed at any time, even du ring full operation of the can nodes. ? a powerful, command driven list controller manages th e organization of the list structure and ensures consistency of the list. ? message fifos are based on the list stru cture and can easily be scaled in size during can operation.
TC1115 functional description data sheet 45 v1.0, 2005-02 advance information ? static allocation commands o ffer compatibility with tw incan applications, which are not list based. ? advanced interrupt handling: ? up to 16 interrupt output lines are available. most interrupt requests can be individually routed to one of the 16 interrupt output lines. ? message postprocessing notif ications can be flexibly aggregated into a dedicated register field of 25 6 notification bits.
TC1115 functional description data sheet 46 v1.0, 2005-02 advance information 3.13 micro link serial bus interface (mli) figure 3-9 shows a global view of the functional blocks of two micro link serial bus interfaces (mli0 and mli1). figure 3-9 general block diagram of the mli0 and mli1 interfaces interrupt control mli_inter fac es cl ock control address decoder f ml i0 mli interface mli0 modul e (kernel ) treadya port 0 control tvalida tdata tclk rreadya rvalida rdataa rclka p0.8/ tclk0a p0.9/ tready0a p0.10/ tvalid0a p0.11/ tdata0a p0.12/rclk0a p0.13/ rready0a p0.14/ rvalid0a p0.15/ rdata0a dma int_o [3:0] int_o [7:4] treadyb port 4 control tvalidb tdata tclk rreadyb rvalidb rdatab rclkb p4.0/ tclk0b p4.1/ tready0b p4.2/ tvalid0b p4.3/ tdata0b p4.4/rclk0b p4.5/ rready0b p4.6/ rvalid0b p4.7/ rdata0b interrupt control cl ock control address decoder f ml i1 mli interface mli1 modul e (kernel ) treadya port 3 control tvalida tdata tclk rreadya rvalida rdataa rclka p3.8 /tclk1 p3.9 / tready1a p3.10 / tvalid1a p3.11 / tdata1 p3.12/ rclk1a p3.13 / rready1a p3.14 / rvalid1a p3.15 / rdata1a dma int_o [1:0] int_o [7:4]
TC1115 functional description data sheet 47 v1.0, 2005-02 advance information the micro link serial bus interface is de dicated to the serial communication between the other infineon 32-bit cont rollers with mli. the communica tion is intende d to be fast due to an address translatio n system, and it is not necessary to have any special program in the second controller. features: ? serial communication from th e mli transmitter to mli rece iver of another controller ? module supports connection of each mli with up to four mli from other controllers ? fully transparent read/write access supported (= remote programming) ? complete address range of ta rget controll er available ? special protocol to tran sfer data, address offset, or address offset and data ? error control using a parity bit ? 32-bit, 16-bit, and 8-bit data transfers ? address offset width: from 1- to 16-bit ? baud rate: f mli / 2 (symmetric shift clock approach), baud rate definition by the co rresponding fracti onal divider
TC1115 functional description data sheet 48 v1.0, 2005-02 advance information 3.14 general purpose timer unit (gptu) figure 3-10 shows a global view of the functional blocks of the general purpose timer unit (gptu). figure 3-10 general block diagra m of the gptu interface the gptu consists of three 32 -bit timers designed to so lve such application tasks as event timing, event counting , and event recording. the gptu communicates with the external world via eight i/o lines located at port 0. the three timers of gptu module, t0, t1 and t2, can operate independently of each other or can be combined: general features: ? all timers are 32-bit precision time rs with a maximum input frequency of f gptu ? events generated in t0 or t1 c an be used to trigger actions in t2 ? timer overflow or underflow in t2 ca n be used to cloc k either t0 or t1 ? t0 and t1 can be concatenated to form one 64-bit timer features of t0 and t1: ? each timer has a dedicated 32-b it reload register with au tomatic reload on overflow ? timers can be split into indi vidual 8-, 16-, or 24-bit ti mers with individual reload registers clock control address decoder interrupt control f gptu0 gptu module port 0 control p0.0/gptu_0 sr0 sr1 sr2 sr3 sr4 sr5 sr6 sr7 in0 in1 in2 in3 in4 in5 in6 in7 out0 out1 out2 out3 out4 out5 out6 out7 p0.1/gptu_1 p0.2/gptu_2 p0.3/gptu_3 p0.4/gptu_4 p0.5/gptu_5 p0.6/gptu_6 p0.7/gptu_7
TC1115 functional description data sheet 49 v1.0, 2005-02 advance information ? overflow signals can be selected to generate service requests, pin output signals, and t2 trigger events ? two input pins can define a count option features of t2: ? count up or down is selectable ? operating modes: ?timer ? counter ? quadrature counter (incremental/p hase encoded c ounter interface) ? options: ? external start/stop, one-shot operati on, timer clear on external event ? count direction control through software or an external event ? two 32-bit reload/ capture registers ? reload modes: ? reload on overflow or underflow ? reload on external event: pos itive transition, ne gative transition, or both transitions ? capture modes: ? capture on external event: positive tr ansition, negative transition, or both transitions ? capture and clear timer on external even t: positive transition, negative transition, or both transitions ? can be split into two 16-bit counter/timers ? timer count, reload, capture, and trigger functi ons can be assigned to input pins. t0 and t1 overflow events can also be assigned to these functions. ? overflow and underflo w signals can be used to trigge r t0 and/or t1 and to toggle output pins ? t2 events are freely assignable to the se rvice request nodes.
TC1115 functional description data sheet 50 v1.0, 2005-02 advance information 3.15 capture/compare unit 6 (ccu6) figure 3-11 shows a global view of the functional blocks of two capture/compare units (ccu60 and ccu61). both of the ccu6 modul es are further supplie d by clock control, interrupt control, address decoding, and port control logic. one dma request can be generated by each ccu6 module. each ccu6 provides two ind ependent timers (t12 , t13), which can be used for pwm generation, especially for ac-m otor control. additionally, sp ecial control modes for block commutation and multi-phas e machines are supported. timer 12 features: ? three capture/compare channel s, each channel c an be used either as capture or as compare channel. ? generation of a three-phase pwm supported (six output s, individual signals for highside and lows ide switches) ? 16-bit resolution, ma ximum count frequency = peripheral clock ? dead-time control for each channel to avoid short-ci rcuits in the power stage ? concurrent update of the required t12/13 registers ? center-aligned and edge-al igned pwm can be generated ? single-shot mode supported ? many interrupt request sources ? hysteresis-like control mode timer 13 features: ? one independent compare channel with one output ? 16-bit resolution, ma ximum count frequency = peripheral clock ? can be synchr onized to t12 ? interrupt generation at pe riod-match and compare-match ? single-shot mode supported additional features: ? block commutation for brushless dc-drives implemented ? position detection vi a hall-sensor pattern ? automatic rotational speed me asurement for block commutation ? integrated error handling ? fast emergency stop without cpu l oad via external signal (ctrap ) ? control modes for mu lti-channel ac-drives ? output levels can be selected and adapted to th e power stage
TC1115 functional description data sheet 51 v1.0, 2005-02 advance information figure 3-11 general block diag ram of the ccu6 interfaces interrupt control TC1115_ccu6_imple ccu60 module (kernel) port 2 control to dma cl ock control address decoder f ccu to dma src0 src1 src2 src3 p2.6 /cc600 p2.12 /ctrap0 cc62 cout62 cout61 cout63 cc60 cout60 ccpos2 cc61 /ctrap ccpos0 ccpos1 p2.13 /ccpos00 p2.14 /ccpos01 p2.15 /ccpos02 p2.7 /cout600 p2.8 /cc601 p2.9 /cout601 p2.10 /cc602 p2.11 /cout602 p2.5 /cout603 ccu61 module (kernel) port 3 control p3.1 /cc610 p3.7 /ctrap1 cc62 cout62 cout61 cout63 cc60 cout60 ccpos2 cc61 /ctrap ccpos0 ccpos1 p3.8 /ccpos10 p3.9 /ccpos11 p3.10 /ccpos12 p3.2 /cout610 p3.3 /cc611 p3.4 /cout611 p3.5 /cc612 p3.6 /cout612 p3.0 /cout613 src0 src1 src2 src3 p0.5 /ccu60_t12hr p0.6 /ccu60_t13hr t12hr t13hr p3.11 / ccu61_t12hr p3.12 / ccu61_t13hr t12hr t13hr
TC1115 functional description data sheet 52 v1.0, 2005-02 advance information 3.16 system timer the stm within the tc 1115 is designed for global system timing applications requiring both high precision and lo ng range. the stm provides the following features: ? free-running 56 -bit counter ? all 56 bits can be read synchronously ? different 32-bit portions of the 56 -bit counter can be read synchronously ? flexible interrupt gene ration on partial stm content compare match ? driven by clock f stm after reset (default after reset is f stm = f sys = 150 mhz) ? counting starts automatica lly after a reset operation ? stm is reset under following reset causes: ? wake-up reset (pmg_con.dsrw must be set) ? software reset (rst_req .rrstm must be set) ? power-on reset ? stm (and the clock divider) is not reset at watch dog reset and hardware reset (hdrst = 0) the stm is an upward counter, runnin g with the system clock frequency f sys (after reset f stm = f sys ). it is enabled per default after rese t, and immediately starts counting up. other than via reset, it is not possible to affect the contents of the timer during normal operation of the application; it can only be read, but not written to. depending on the implementation of the clock co ntrol of the stm, the timer ca n optionally be disabled or suspended for power-saving and debugging pur poses via a clock control register. the maximum cloc k period is 2 56 / f stm . at f stm = 150 mhz (maximum), for example, the stm counts 15.2 years before overflowing. thus , it is capable of co ntinuously timing the entire expected product lifetime of a system without overflowing.
TC1115 functional description data sheet 53 v1.0, 2005-02 advance information figure 3-12 block diagram of the stm module stm module 00 h cap tim6 tim5 tim4 tim3 tim2 tim1 tim0 00 h 55 47 39 31 23 15 7 56-bit system timer address decoder clock control enable / disable f stm mca04795_mod 31 23 15 7 compare register cmp0 interrupt control compare register cmp1 stmir1 stmir0 porst 0 0 31 23 15 7 0
TC1115 functional description data sheet 54 v1.0, 2005-02 advance information 3.17 watchdog timer the watchdog timer (w dt) provides a highly reliable and secure way to detect and recover from software or hardware failure. the wd t helps to abor t an accidental malfunction of the tc 1115 in a user-specified time per iod. when enabled, the wdt will cause the TC1115 system to be reset if the wdt is not serviced within a user-programmable time period. the cpu must service the wd t within this time interval to prevent the wdt from causi ng a TC1115 system reset. he nce, routine service of the wdt confirms that the system is functioning properly. in addition to this standar d ?watchdog? function, the wdt incorpor ates the endinit feature and monitors its modifi cations. a system-wide line is connected to the endinit bit implemented in a wdt contro l register, serving as an a dditional write-protection for critical registers (besides supervisor mode pr otection). registers pr otected via this line can be modified only when supervisor mode is acti ve and bit endinit = 0. a further enhancement in the TC1115?s watchdog timer is its reset prewarning operation. instead of immediat ely resetting the device upon detection of an error, the wdt first issues a non-maskable interrupt (n mi) to the cpu before finally resetting the device at a specified time period later. this gives the cpu a chance to save system state to memory for later examinat ion of the cause of the malf unction, thus providing an important aid in debugging. features: ? 16-bit watchdog counter ? selectable input frequency: f sys /256 or f sys /16384 ? 16-bit user-definable reload value for norm al watchdog operation, fixed reload value for time-out and prewarning modes ? incorporation of the endinit bit and monitoring of its modifications ? sophisticated password ac cess mechanism with fixed and user-definable password fields ? proper access always requires two writ e accesses. the time between the two accesses is monitored by the wdt. ? access error detection: invalid password (during first access) or invalid guard bits (during second access) trigge r the watchdog re set generation. ? overflow error detection: an overflow of the counter trigger s the watchdog reset generation. ? watchdog function can be di sabled; access protection and endinit mo nitor function remain enabled. ? double reset detection: if a watchdog induced reset oc curs twice without a proper access to its control register in between, a severe system malfun ction is assumed and the TC1115 is held in reset until a power-on rese t. this prevents the device from being periodically reset i f, for instance, connec tion to the external memory ha s been lost such that even system initiali zation could not be performed.
TC1115 functional description data sheet 55 v1.0, 2005-02 advance information ? important debugging support is provided through the reset prewarning operation by first issuing an nmi to the cp u before finally resetting the device after a certain period of time.
TC1115 functional description data sheet 56 v1.0, 2005-02 advance information 3.18 system control unit the system control unit (scu) of the TC1115 handles the system control tasks. all of these system functions are tightly coupled; th us, they are convenie ntly handled by one unit, the scu. the system tasks of the scu are: ?clock control ? clock generation ? oscillator and pll control ? reset and boot control ? generation of all in ternal reset signals ? generation of exte rnal hardware and software reset signal ? power management control ? enabling of several power management modes ? configuration input sampling ? fpu interrupts ? external request unit ? parity error control ? fault sram fuse box ? cscomb control ? ebu pull-up control ? nmi control and status ? dma request signal selection
TC1115 functional description data sheet 57 v1.0, 2005-02 advance information 3.19 boot options the TC1115 booting schemes prov ides a number of different boot options for the start of code execution. table 3-3 shows the boot options av ailable in the TC1115. table 3-3 boot selections brkin 1) 1) this input signal is active low. tm 1) hwcfg [2:0] type of boot pc start value (user entry) 11000 bootstrap loader serial boot from asc to pmi scratch pad, run loaded program dfff fffc h 2) (d400 0000 h ) 2) this is the bootrom entry address; the star t address of user program in parentheses. 001 bootstrap loader serial boot from can to pmi scratch pad, run loaded program 010 bootstrap loader serial boot from ssc to pmi scratch pad, run loaded program 011 external memory, ebu as master dfff fffc h 2) (a000 0000 h ) 100 external memory, ebu as slave dfff fffc h 2) (a000 0000 h ) 101 reserved (stop) ---- 110 pmi scratch pad d400 0000 h 111 reserved (stop) dfff fffc h 2) 1 0 000-111 reserved (stop) dfff fffc h 2) 0 1 000 tristate chip ---- 001 go to external em ulator space dfff fffc h 2) (de00 0000 h ) 010 reserved (stop) ---- 011 osc and pll bypass ---- 100-111 reserved (stop) dffffffc h 2) 0 0 000-111 reserved (stop) dffffffc h 2)
TC1115 functional description data sheet 58 v1.0, 2005-02 advance information 3.20 power management system the TC1115 power man agement system allows softwa re to configur e the various processing units to adj ust automatically in order to dr aw the minimum necessary power for the application. there are four powe r manageme nt modes: ? run mode ? idle mode ? sleep mode ? deep sleep mode table 3-4 describes the features of the power management modes. besides these expl icit software-controlled power-sav ing modes, specia l attention has been paid in the tc11 15 to automatic power-s aving in operating un its that are currently not required or idle. in this case, they are shut off automatically until their operation is required again. table 3-4 power managem ent mode summary mode description run the system is fully oper ational. all clocks and peripherals are enabled, as determined by software. idle the cpu clock is disabled, waiting for a condition to return it to run mode. idle mode can be entered by softwar e when the processo r has no active tasks to perform. all peripherals re main powered and cl ocked. processor memory is accessible to peripherals . a reset, watchdog timer event, a falling edge on the nmi pin, or any enabled interru pt event will return the system to run mode. sleep the system clock continue s to be distributed only to those peripherals programmed to operate in sleep mode. the other pe ripheral modules will be shut down by the suspend signal. interru pts from operating peripherals, the watchdog timer, a falling edge on the nmi pin, or a reset event will return the syst em to run mode. entering this state requires an orderly shut-down contro lled by the power man agement state machine. deep sleep the system clock is sh ut off; only an external signal will restart the system. entering this state requires an orderly shut-d own controlled by the power management state machine (pmsm).
TC1115 functional description data sheet 59 v1.0, 2005-02 advance information 3.21 on-chip debug support the on-chip debug support of the TC1115 co nsists of the follow ing building blocks: ? ocds l1 module of tricore? ? ocds l2 interface of tricore? ? ocds l1 module in th e bcu of the fpi bus ? ocds l1 facilities within the dma ? ocds l2 interface of dma ? ocds system control unit (oscu) ? multi core break switch (mcbs) ? jtag based debug interface (cerberus jdi) ? suspend functionality of peripherals features: ? tricore? l1 ocds: ? hardware event generation unit ? break by debug instru ction or break signal ? full single-step support in hardware , possible also wi th software break ? access to memory, sf rs, etc. on the fly ? dma l1 ocds: ? output break request on errors ? suspension of pre-selected channels ? level 2 trace port with 16 pins that outputs either tricore?, or dma trace ? ocds system control unit (cerberus oscu) ? minimum number of pins required (no ocds enable pin) ? hardware allows hot attach of a debugger to a running system ? system is secure (can be locked from internal) ? multi core break switch (cerberus mcbs): ? tricore?, dma, break pins, and bcus as break sources ? tricore? as break targets; other parts can in addit ion be suspended ? synchronous stop and restart of the system ? break to susp end converter figure 3-13 shows a basic block diagra m of the buil ding blocks.
TC1115 functional description data sheet 60 v1.0, 2005-02 advance information . figure 3-13 ocds support basic block diagram enab le , con tro l and reset bcu tricore tm ocds l1 ocds l2 ocds l1 dma fpi wat ch- dog timer periph.1 periph.n jdi debug i/f jtag controller mcbs break switch ce rb er u s oscu break and suspe nd si gna ls multiplexer dma l2 16 brkin tdi tdo brkout trst tms tck ocds2[15:0]
TC1115 functional description data sheet 61 v1.0, 2005-02 advance information 3.22 clock generation unit the clock generation unit (cgu) allows a flexible clock generation for TC1115. the power consumption is indirectly proportional to the frequency, wher eas the performance of the microcontroller is directly proportion al to the frequency. during user program execution the frequency can be programmed for an optimal ratio between performance and power consumption. there fore, the power consumption can be adapted to the actual application state. features: the clock generation unit serves several purposes: ? pll feature for multiplying clo ck source by different factors ? direct drive for direct clock input ? comfortable state machine for secure switching between basic pll, direct, or prescaler operation ? sleep and power-do wn mode support the clock generati on unit in the TC1115, shown in figure 3-14 , consists of an oscillator circuit and one phase-locked loop (pll). the pll can conver t a low-frequency external clock signal to a high-speed internal clock fo r maximum performance. the pll also has fail-safe logi c that detects degenerate external clock behavior su ch as abnormal frequency deviations or a tota l loss of the external cloc k. it can execute emergency actions if it looses the lo ck on the external clock. in general, the clock generati on unit (cgu) is controlled through the system control unit (scu) module of the TC1115. figure 3-14 clock generation unit block diagram 1 > mca04940mod oscillator circui t xtal1 xtal2 f osc phase detect. vco n divider pll f vco 1 0 1:1/1:2 di vi der f sys lock detector oscr pll_ lock ndiv [6:0] vco_ bypass kdiv [3:0] pll_ bypass system control unit scu register pll_clc mux mux k:1/k:2 di vi der vco_ sel[1:0] f cpu sys fsl clock generation unit cgu p di vi - der osc. run detect. pdiv [2:0] osc disc register osc_con mosc ogc
TC1115 functional description data sheet 62 v1.0, 2005-02 advance information the oscillator circuit, wh ich is designed to work with an external cr ystal oscillator or an external stable clock source, consists of an inverting ampl ifier with xtal 1 as input and xtal2 as output. figure 3-15 shows the recommended exte rnal oscillator circui tries for both operating modes, i.e. external crystal mode and external input clock mode. figure 3-15 oscillator circuitries when using an external clock signal, it must be connected to xtal1 and xtal2 is left open (unconnected). when s upplying the clock signal dire ctly, not using a crystal and the oscillator, the input frequen cy can be in the range of 0 - 40 mhz if the pll is not used, 4 - 40 mhz in case the pll is used. when using a crystal, its fr equency can be with in the range of 4 mhz to 25 mhz. an external oscillator load circuitry must be used, connected to both pins, xtal1 and xtal2. it consists normally of the two load capacitances, c1 and c2. for some crystals, a series damp resistor may be necessary. the exac t values and related operating range are dependant on the crystal an d have to be determined an d optimized toget her with the crystal vendor using t he negative resistance me thod. as starting point for the evaluation and for non-productive system s, the following load capacitor values might be used. table 3-5 load capacitors select fundamental mode crystal frequency (approx., mhz) load capacitors c1, c2 (pf) 433 818 12 12 16 10 TC1115 oscillator v ddo sc v ssosc c 1 4 - 25 mhz c 2 xtal1 xtal2 TC1115 oscillator v ddo sc v ssosc xtal1 xtal2 external clock signal f osc f osc fundamental mode crystal v ddo sc3 v ddo sc3 osc_cedar_TC1115
TC1115 functional description data sheet 63 v1.0, 2005-02 advance information a block capacitor between v ddosc3 and v ssosc , v ddosc and v ssosc is recommended, too. 20 10 24 10 table 3-5 load capacitors select (cont?d) fundamental mode crystal frequency (approx., mhz) load capacitors c1, c2 (pf)
TC1115 functional description data sheet 64 v1.0, 2005-02 advance information 3.23 power supply the TC1115 provides an ingenious power su pply concept in order to improve the emi behavior as well as to minimize the crosstalk within on-chip modules. figure 3-16 shows the TC1115?s power supply concept, where cert ain logic modules are individually supplied with power. this concept improves the emi behavior by reduction of the noi se cross coupling. figure 3-16 TC1115 po wer supply concept mcb04953mod dmu dmi pmi cpu & peripheral logic gpio ports (p0-p4) ebu ports osc v ddo sc3 (3.3v) v ss v ddo sc (1.5v) v ss v ddp (3.3 v) v ss v ss (1.5 v) v dd
TC1115 functional description data sheet 65 v1.0, 2005-02 advance information 3.24 power sequencing during power-up, reset pin porst has to be held active until both power supply voltages have reached at le ast their minimum values. during the power-up time (rising of the supply voltages from 0 to their regular operating values), it must be ensured, that the core v dd power supply reaches its operating value first, and then follow ed by the gpio v ddp power supply. during t he rising time of the core voltage, it must be ensured that 0< v dd -v ddp <0.5 v. during power-down, the core power supply v dd and gpio power supply v ddp must be switched off completely unti l all capacitances are discharged to zero before the next power-up. note: the state of the pins are unde fined when only the port voltage v ddp is switched on.
TC1115 functional description data sheet 66 v1.0, 2005-02 advance information 3.25 identification register values table 3-6 TC1115 identification registers short name address value scu_id f000 0008 h 002c c001 h manid f000 0070 h 0000 1820 h chipid f000 0074 h 0000 8c01 h rtid f000 0078 h 0000 0000 h sbcu_id f000 0108 h 0000 6a0a h stm_id f000 0208 h 0000 c005 h cbs_jdpid f000 0308 h 0000 6307 h gptu_id f000 0608 h 0001 c002 h ccu60_id f000 2008 h 0042 c004 h ccu61_id f000 2108 h 0042 c004 h dma_id f000 3c08 h 001a c011 h can_id f000 4008 h 002b c022 h ssc0_id f010 0108 h 0000 4530 h ssc1_id f010 0208 h 0000 4530 h asc0_id f010 0308 h 0000 44e2 h asc1_id f010 0408 h 0000 44e2 h asc2_id f010 0508 h 0000 44e2 h iic_id f010 0608 h 0000 4604 h mli0_id f010 c008 h 0025 c004 h mli1_id f010 c108 h 0025 c004 h mchk_id f010 c208 h 001b c001 h cps_id f7e0 ff08 h 0015 c006 h mmu_id f7e1 8008 h 0009 c002 h cpu_id f7e1 fe18 h 000a c005 h ebu_id f800 0008 h 0014 c004 h dmu_id f800 0408 h 002d c001 h dmi_id f87f fc08 h 0008 c004 h pmi_id f87f fd08 h 000b c004 h
TC1115 functional description data sheet 67 v1.0, 2005-02 advance information lbcu_id f87f fe08 h 000f c005 h lfi_id f87f ff08 h 000c c005 h table 3-6 TC1115 identification registers (cont?d) short name address value
TC1115 electrical parameters data sheet 68 v1.0, 2005-02 advance information 4 electrical parameters 4.1 general parameters 4.1.1 parameter interpretation the parameters listed in this section repr esent partly the characte ristics of the TC1115 and partly its requirements on the system. to aid interpre ting the parameters easily when evaluating them for design purposes, they are indicated by the abbrevia tions in the ?symbol? column: ? cc these parameters indicate c ontroller c haracteristics, which are distinctive features of the TC1115 and must be considered fo r system design. ? sr these parameters indicate s ystem r equirements, which mu st be provided by the microcontroller system in which the tc11 15 is included.
TC1115 electrical parameters data sheet 69 v1.0, 2005-02 advance information 4.1.2 absolute maximum rating note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditio ns above thos e indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maxi mum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absol ute maximum ratings. parameter symbol limit values unit notes min. max. ambient temperature t a -40 85 c under bias storage temperature t st -65 150 c? junction temperature t j -40 125 c under bias voltage at 1.5 v power supply pins with respect to v ss 1) 1) applicable for v dd and v ddosc . v dd -0.5 1.7 v ? voltage at 3.3 v power supply pins with respect to v ss 2) 2) applicable for v ddp and v ddosc3 . the maximum voltage difference must not exceed 4.0 v in any case (i.e. supply voltage = 4.0 v and input voltage = -0.5 v is not allowed). v ddp -0.5 4.0 v ? voltage on any pi n with respect to v ss 2) v in -0.5 4.0 v ? input current on any pin during overload condition i in -10 10 ma ? absolute sum of all input currents during overload condition i in ? |100| ma ? cpu & lmb bus frequency f sys ?150mhz? fpi bus frequency f fpi ?100mhz?
TC1115 electrical parameters data sheet 70 v1.0, 2005-02 advance information 4.1.3 operating condition the following operating conditions must be complied with in or der to ensure correct operation of the TC1115 . all parameters specif ied in the following table refer to these operating conditions, unle ss otherwise indicated. parameter symbol limit values unit notes conditions min. max. digital supply voltage v dd 1.43 1.58 v ? v ddp 3.14 3.47 v ? digital ground voltage v ss 0v? digital core supply current i dd ?525ma? ambient temperature under bias t a -40 +85 c? cpu clock f sys ? 1) 1) the TC1115 uses a static design, so the minimum oper ation frequency is 0 mhz. however, due to test time restriction no lower frequency boundary is tested. 150 mhz ? overload current i ov -1 1 ma 2)3) 2) overload conditions occur if the standard operating condi tions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v ddp + 0.5 v or v ov < v ss - 0.5 v). the absolute sum of input overload currents on all digital i/o pins may not exceed 50 ma . the supply voltage must remain within the specified limits. 3) not subject to production test, verified by design/characterization. -3 3 duty cycle 25% short circuit current i sc -1 1 ma 4) 4) applicable for digital inputs. -3 3 duty cycle 25% absolute sum of overload + short circuit currents | i ov |+ | i sc | ?|50|ma 3) |100| duty cycle 25% inactive device pin current (v dd =v ddp =0) i id -1 1 ma ? external load capacitance c l ?50pf? esd strength ? 2000 ? v human body model (hbm)
TC1115 electrical parameters data sheet 71 v1.0, 2005-02 advance information 4.2 dc parameters 4.2.1 input/output characteristics v ss = 0 v; t a = -40 c to +125 c parameter symbol limit valu es unit test condition min. max. gpio pins, dedicated pins and ebu pins input low voltage v il sr -0.3 0.8 v lvttl input high voltage v ih sr 2.0 v ddp + 0.3 vlvttl output low voltage v ol cc ? 0.4 v i ol = 2ma output high voltage v oh cc 2.4 ? v i oh = -2ma pull-up current 1) 1) the current is applicable to the pins, for which a pull-up has been specified. refer to table 2-1 . i pu x refers to the pull-up current for type x in absolute values . |i pua | cc ?149 a v in = 0v |i puc | cc ?7.2 a v in = 0v pull-down current 2) 2) the current is applicable to the pins, for which a pull-down has been specified. refer to table 2-1 . i pd x refers to the pull-down current for type x in absolute values . |i pda | cc ? 156 a v in = v ddp |i pdc | cc ? 15.7 a v in = v ddp input leakage current 3) 3) excluded following pins: nmi , trst , tck, tdi, tms, ale, p2.1, hwcfg0, hwcfg1, hwcfg2, brkin, porst, hdrst. i oz1 cc ? 350 na 0 < v in < v ddp pin capacitance 4) 4) not subject to production test, verified by design/characterization c io cc ? 10 pf f = 1 mhz t a = 25 c
TC1115 electrical parameters data sheet 72 v1.0, 2005-02 advance information 4.2.2 oscillator characteristics v ss = 0 v; t a = -40 c to +125 c parameter symbol limit valu es unit test condition min. max. oscillator pins input low voltage at xtal1 v ilx sr -0.3 ? v 1) 1) quartz mode: using a quartz crystal input high volt age at xtal1 v ihx sr ? 3 v 1) quartz oscillation peak-peak amplitude at oscillator input v pposc sr 0.6 ? v 1) input low voltage at xtal1 v ilx sr -0.3 0.1 v 2) 2) bypass mode: using an external clock input high volt age at xtal1 v ihx sr 1.4 v ddc + 0.3v v 2) oscillator input current i oscin ?25 a
TC1115 electrical parameters data sheet 73 v1.0, 2005-02 advance information 4.2.3 iic characteristics each iic pin is an open drain output pin with different characteristics than other pins. the related characteristics are gi ven in the following table. note: no 5 v iic interface is su pported with these pads. only voltages lower than 3.63 v must be applied to these pads. note: iic pins have no pul l-up and pull-down devices. parameter symbol limit values unit test conditions min. max. output low voltage v ol cc ? 0.4 0.6 v3 ma sink current 6 ma sink current input high voltage 1) 1) not subject to production test, verified by design/characterization. v ih sr 0.7v ddp v ddp +0.5 v ? input low voltage 1) v il sr -0.5 0.3v ddp v?
TC1115 electrical parameters data sheet 74 v1.0, 2005-02 advance information 4.2.4 power supply current parameter symbol limit va lues unit test conditions typ. 1) 1) typical values are measured at 25c, cpu clock at 150 mhz, and nominal supply voltage that is 3.3 v for v ddp , v ddosc3 and 1.5 v for v dd , v ddosc . these currents are measured using a typical application pattern. the power consumption of modules can increase or decrease using other application programs. max. active mode supply current i dd 314 679 ma sum of i dds 2) 2) these power supply currents are defined as the sum of all currents at the v dd power supply lines: v dd + v ddp + v ddosc3 + v ddosc 153 345 ma i dd at v dd 3) 3) this measurement includes the tricore tm and logic power supply lines. 156 322 ma i dd at v ddp idle mode su pply current i id 74 154 ma sum of i dds 2)4) 4) cpu is in idle state, input clocks to all peripherals are enabled. 66 130 ma i dd at v dd 3)4) 615ma i dd at v ddp 4) deep sleep m ode supply current i ds 2 19 ma sum of i dds 2)5) 5) clock generation is disabled at the source. 219ma i dd at v dd 3)5) 3.6 58 a i dd at v ddp 5)
TC1115 electrical parameters data sheet 75 v1.0, 2005-02 advance information 4.3 ac parameters 4.3.1 power, pad and reset timing parameter symbol limit values unit min. max. min. v ddp voltage to ensure defined pad states 1) 1) this parameter is valid under assumption that porst si gnal is constantly at low level during the power-up/ power-down of the v ddp . v ddppa cc 0.6 ? v oscillator start-up time 2) 2) not subject to production test, verified by design/characterization. t oscs cc ? 30 ms minimum porst active time after power supplies are st able at operating levels t poa cc 50 ? ms h d rst pulse width t hd cc 1024 cycles 3) 3) any hdrst activation is internally prolonged to 1024 fpi bus clock cycles. f sys ports inactive after any reset active 2) t pi cc ? 30 ns
TC1115 electrical parameters data sheet 76 v1.0, 2005-02 advance information figure 4-1 power and reset timing reset_beh 1) as programmed vddp porst hdrst pads pad- state undefined t pi vdd v ddppa v ddppa pad- state undefined 2) tri-state, pull device active t hd v ddpr osc t oscs 1) 2) 1) 2) 2) t poa t poa t hd
TC1115 electrical parameters data sheet 77 v1.0, 2005-02 advance information 4.3.2 pll parameters when pll operation is configured ( pll_clc.lock = 1 ), the on-chip phase locked loop is enabled and prov ides the master clock. the pll multiplies the input frequency by the factor f ( f mc = f osc f ) which results from the input divi der, the multiplication factor (n factor), and the output divider ( f = ndiv+1 / (pdiv+1 kdiv+1) ). the pll circuit synchronizes the master clock to the input clock. this synchronizatio n is done smoothly, i.e. the master clock frequency does not chan ge abruptly. due to this adaptati on to the input clock, the frequency of f mc is constantly adjusted so it is locked to f osc . the slight variati on causes a jitter of f mc which also affects the duration of individual tcms. the timing listed in the ac charac teristics refers to tcps. because f cpu is derived from f mc , the timing must be calculated using th e minimum tcp possible under the respective circumstances. the actual minimum value for tcp depends on the jitter of the pll. as the pll is constantly adjusting its outp ut frequency in order to correspond to the applied input frequency (crystal or oscillator), the relative deviation for periods of more than one tcp is lower than for one sing le tcp (see formula and figure 4-2 ). this is especially importan t for bus cycles using waitst ates and for the operation of timers, serial interfaces, etc. for all slower operations and l onger periods (e.g. pulse train generation or measur ement, lower baud rates, etc.) th e deviation caused by the pll jitter is negligible. the value of the accumulated pll jitter depends on the number of consecutive vco output cycles within the resp ective timeframe. the vco outp ut clock is divided by the output prescaler (k = kdiv +1) to generate the master clock signal f mc . therefore, the number of vco cycles ca n be represented as k n , where n is the number of consecutive f mc cycles (tcm). for a period of n tcm, the accumulated pll jitter is defined by the corresponding deviation d n : d n [ns] = (1.5 + 6.32 n / f mc ); f mc in [mhz], n = number of consecutive tcms. so, for a period of 3 tcm s @ 20 mhz and k = 12: d 3 = (1.5 + 6.32 3 / 20) = 2.448 ns. this formula is applicable for k n < 95. for longe r periods, the k n =95 value can be used. this steady value ca n be approximated by: d n max [ns] = (1.5 + 600 / (k f mc )).
TC1115 electrical parameters data sheet 78 v1.0, 2005-02 advance information figure 4-2 approximated accumulated pll jitter note: the bold lines indicate the minimum accumulated jitter whic h can be achieved by selecting the maximu m possible output prescaler factor k. different frequency bands can be selected for the vco, so th e operation of the pll can be adjusted to a wide range of input and output frequencies: table 4-1 vco bands for pll operation pll_clc.vcosel vco frequency ra nge base frequency range 1) 1) base frequency range is the free running operation frequency of the pll, when no input clock is available. 00 400 ... 500 mhz 250 ... 320 mhz 01 500 ... 600 mh z 300 ... 400 mhz 10 600 ... 700 mh z 350 ... 480 mhz 11 reserved 2) 2) this option cannot be used. mcb04413_xc.vsd acc. jitter d n 8 6 ns 4 2 1 0 510 20 25 n 1 0 m h z k=5 2 0 m h z 4 0 m h z 7 5 3 15 k=6 k=12 k=15 k=8 k=10 1
TC1115 electrical parameters data sheet 79 v1.0, 2005-02 advance information 4.3.3 ac characteristics (operating conditions apply) figure 4-3 input/output waveforms for ac tests - for gpio, dedicated and ebu pins 2.0v 0.8v test points 2.0v 0.8v 2.4v 0.4v ac inputs during testing are driven at 2.4v for a logic ?1? and 0.4v for a logic ?0?. timing measurements are made at v ihmin for a logic ?1? and v ilmax for a logic ?0?.
TC1115 electrical parameters data sheet 80 v1.0, 2005-02 advance information 4.3.4 input clock timing (operating conditions apply) figure 4-4 input clock timing parameter symbol limits unit min max oscillator clock frequency with pll f osc sr 4 25 mhz input clock freque ncy driving at xtal1 with pll f oscdd sr -40mhz input clock du ty cycle ( t 1 / t 2 ) sr4555% input clock at xtal1 t 1 0.5 v dd t 2 t oscdd v ihx v ilx
TC1115 electrical parameters data sheet 81 v1.0, 2005-02 advance information 4.3.5 port timing (operating conditions apply; c l =50 pf) figure 4-5 port timing parameter symbol limits unit min max port data valid from trclk 1) up to 120 mhz 2) 1) port data is output with respect to the fpi clock. the trclk is used as a reference here since the fpi clock is not available as an external pin and trclk is same frequency as cpu clock. port lines maintain their states for at least 2 cpu clocks. 2) 120 mhz is verified by design/characterization. t 1 cc ? 13 ns trclk old state new state t 1 port lines fpi_clk
TC1115 electrical parameters data sheet 82 v1.0, 2005-02 advance information 4.3.6 timing for jtag signals (operating conditions apply; c l =50 pf) figure 4-6 tck clock timing parameter symbol limits unit min max tck clock period t tck sr 50 ? ns tck high time t 1 sr 10 ? ns tck low time t 2 sr 29 ? ns tck clock rise time t 3 sr ? 0.4 ns tck clock fall time t 4 sr ? 0.4 ns tck t 4 0.9 v dd t 3 t 1 0.1 v dd t 2 t tck 0.5 v dd
TC1115 electrical parameters data sheet 83 v1.0, 2005-02 advance information figure 4-7 jtag timing parameter symbol limits unit min max tms setup to tck t 1 sr 7.85 ? ns tms hold to tck t 2 sr 3.0 ? ns tdi setup to tck t 1 sr 10.9 ? ns tdi hold to tck t 2 sr 3.0 ? ns tdo valid output from tck t 3 cc ? 10.7 ns tdo high impedance to va lid output from tck t 4 cc ? 23.0 ns tdo valid output to high impedan ce from tck t 5 cc ? 26.0 ns tms tdi tck tdo t 1 t 2 t 1 t 2 t 4 t 3 t 5
TC1115 electrical parameters data sheet 84 v1.0, 2005-02 advance information 4.3.7 timing for ocds trace and breakpoint signals (operating conditions apply; c l (trclk) = 25 pf, c l = 50 pf) figure 4-8 ocds trace signals timing parameter symbol limits unit min max brk_out valid from trclk t 1 cc ? 5.2 ns ocds2_status[4:0] valid from trclk t 1 cc 0 5 ns ocds2_indir_pc[7:0] valid from trclk t 1 cc 0 5 ns ocds2_brkpt[2:0] valid from trclk t 1 cc 0 5 ns cpu trace signals trclk t 1 old state new state t 1 note: cpu trace signals include brk_in , brk_out , ocds2_status[4:0] , ocds2_indir_pc[7:0] and ocds_brkpt[2:0] .
TC1115 electrical parameters data sheet 85 v1.0, 2005-02 advance information 4.3.8 ebu timings 4.3.8.1 sdclko output clock timing (operating conditions apply; cl = 50 pf) 4.3.8.2 bfclko output clock timing (operating conditions apply; c l =50 pf) parameter symbol limits 1) 1) the parameters are applicable for pc100 sdram access and the maximum sdclko is up to 100 mhz. limits 2) 2) the parameters are applicable for pc133 sdram access and the maximum sdclko is up to 120 mhz. unit min max min max sdclko period t 1 cc10?8.3?ns sdclko high time t 2 cc 3 ? 2.5 ? ns sdclko low time t 3 cc 3 ? 2.5 ? ns sdclko rise time t 4 cc ? 2.5 ? 2.5 ns sdclko fall time t 5 cc ? 2.5 ? 2.5 ns parameter symbol limit 1) 1) the cpu runs at 150 mhz and the burst flash runs at divided by 3 clock. limit 2) 2) the cpu runs at 120 mhz and the burst flash runs at divided by 2 clock. unit min max min max clock period t 1 cc 20 ? 16.7 ? ns bfclko high time t 2 cc 6.6 ? 7.5 ? ns bfclko low time t 3 cc 6.6 ? 7.5 ? ns bfclko rise time t 4 cc ? 3.5 ? 3.5 ns bfclko fall time t 5 cc ? 2.5 ? 2.5 ns
TC1115 electrical parameters data sheet 86 v1.0, 2005-02 advance information figure 4-9 ebu clock output timing 4.3.8.3 timing for sdram access signals (operating conditions apply; c l =50 pf 1) ) 1) if application conditions other than 50 pf capacitive load are used, then the proper correlation factor should be used for your specific application condition. for design team , the load should be set according to the system requirement. 2) the parameters are applicable for pc100 sdram access and the maximum sdclko is up to 100 mhz. 3) the parameters are applicable for pc133 sdram access and the maximum sdclko is up to 120 mhz. parameter symbol limits 2) limits 3) unit min max min max sdclko period t 1 cc10?8.3?ns cke output valid time from sdclko t 1 cc ? 8.0 ? 6.8 ns cke output hold time from sdclko t 2 cc 0 ? 0.8 ? ns address output valid time from sdclko t 3 cc ? 8.0 ? 6.8 ns address output hold time from sdclko t 4 cc 1.0 ? 0.8 ? ns csx , ras , cas , rd/wr , bc(3:0) output valid time from sdclko t 5 cc ? 8.0 ? 6.8 ns csx , ras , cas , rd/wr , bc(3:0) output hold time from sdclko t 6 cc 1.0 ? 0.8 ? ns ad(31:0) output valid time from sdclko t 7 cc ? 8.0 ? 6.8 ns ad(31:0) output hold time from sdclko t 8 cc 1.0 ? 0.8 ? ns ad(31:0) input setu p time to sdclko t 9 sr 4.0 ? 2.9 ? ns ad(31:0) input hold time from sdclko t 10 sr 3.0 ? 3.0 ? ns bfclko / sdclko t 1 0.5 v dd t 2 t 3 t 5
TC1115 electrical parameters data sheet 87 v1.0, 2005-02 advance information figure 4-10 sdram access timing sdclko cke address row csx ras cas rd/wr bc[3:0] ad[31:0] t 1 t 3 t 5 t 5 t 4 t 6 t 5 t 5 t 6 t 9 column t 6 t 6 t 10 d(0) d(n) sdclko cke address row csx ras cas rd/wr bc[3:0] ad[31:0] t 1 t 3 t 5 t 5 t 4 t 6 t 5 t 7 column t 6 t 6 t 8 d(0) d(n) read access write access t 5 t 6 sdram_timing t 2 t 5 t 6
TC1115 electrical parameters data sheet 88 v1.0, 2005-02 advance information 4.3.8.4 timing for burst flash access signals (operating conditions apply; c l =50 pf) parameter symbol limits unit min max address output valid time from bfclko t 1 cc ? 11.0 ns address output hold time from bfclko t 2 cc 10.0 ? ns csx output valid time from bfclko t 3 cc ? 9.0 ns rd output valid ti me from bfclko t 4 cc ? 10.0 ns adv output valid time from bfclko t 5 cc ? 10.0 ns adv output hold time from bfclko t 6 cc 3.0 ? ns baa output valid time from bfclko t 7 cc ? 10.0 ns baa output hold time from bfclko t 8 cc 3.0 ? ns ad(31:0) input setu p time to bfclko t 9 sr 5.0 ? ns ad(31:0) input hold time from bfclko t 10 sr 3.0 ? ns wait input setup time to bfclko t 11 sr 5.0 ? ns wait input hold time from bfclko t 12 sr 3.0 ? ns
TC1115 electrical parameters data sheet 89 v1.0, 2005-02 advance information figure 4-11 burst fl ash access timing note: output delays are always referenced to bfclko. the refe rence clock for input characteristics depends on bit bfcon.fdbken. bfcon.fdbken = 0: bfclko is the input reference clock. bfcon.fdbken = 1: bfclki is the input reference cl ock (ebulmb clock feedback enabled). bfclko address csx adv rd baa d[31:0] t 1 t 3 t 5 t 6 t 4 t 9 t 11 t 12 t 2 t 7 t 8 t 10 bf_timing address d(0) d(n-1) wait address phase(s) command delay phase(s) command phase(s) burst phase(s) burst phase(s) recovery phase new addr. phase(s)
TC1115 electrical parameters data sheet 90 v1.0, 2005-02 advance information 4.3.8.5 timing for demultiplexed access signals (operating conditions apply; c l =50 pf) 1) 1) the purpose for characterization of asynchronous access is to provide the performance of all of the signals to user. user can decide whether an extra cycle is needed or not based on above parameters to generate signals with correct timing sequence. it is user?s responsibility to program the correct phase length according to the memory/peripheral device specif ication and ebu specification. parameter symbol limits unit min max c sx , rd/wr , rd , mr/w , bc(3:0) output valid time from output clock t 1 cc ? 9ns c sx , rd/wr , rd , mr/w , bc(3:0) output hold time from output clock t 2 cc 0.0 ? ns address output valid ti me from output clock t 3 cc ? 9ns address output hold ti me from output clock t 4 cc 0.0 ? ns wait input setup time to output clock t 7 sr 12 ? ns wait input hold time from output clock t 8 sr 3 ? ns ad(31:0) output valid ti me from output clock t 9 cc ? 9ns ad(31:0) output hold time from output clock t 10 cc 0.0 ? ns ad(31:0) input setup ti me to output clock t 11 sr 1.3 ? ns ad(31:0) input hold ti me from output clock t 12 sr 3 ? ns rmw output valid time from output clock t 13 cc ? 8ns rmw output hold time from output clock t 14 cc 1.3 ? ns ad(31:0) output ho ld time from rd/wr t 16 cc 0 ? ns
TC1115 electrical parameters data sheet 91 v1.0, 2005-02 advance information figure 4-12 demultiplexed asy nchronous device access timing sdclko address address csx rd/wr mr/w cmdelay bc[3:0] ad[31:0] t 3 t 1 t 1 t 4 t 2 t 1 t 9 t 2 t 2 t 10 dataout read access write access t 5 t 6 demux_timing t 1 wait t 7 t 8 t 2 t 1 sdclko/ sdclki address address csx rd mr/w cmdelay bc[3:0] ad[31:0] t 3 t 1 t 1 t 4 t 2 t 1 t 11 t 2 t 2 t 12 datain t 5 t 6 t 2 wait t 7 t 8 t 1 rmw t 13 t 14 address phase(s) command delay phase(s) (int.) command delay phase(s) (ext.) command phase(s) data hold phase(s) recovery phase address phase(s) command delay phase(s) (int.) command delay phase(s) (ext.) command phase(s) recovery phase t 16 t 15 t 15
TC1115 electrical parameters data sheet 92 v1.0, 2005-02 advance information 4.3.8.6 timing for multiplexed access signals (operating conditions apply; c l =50 pf) 1) 1) the purpose for characterization of asynchronous access is to provide the performance of all of the signals to user. user can decide whether an extra cycle is needed or not based on above parameters to generate signals with correct timing sequence. it is user?s responsibility to program the correct phase length according to the memory/peripheral device specif ication and ebu specification. parameter symbol limits unit min max ale, csx , rd/wr , rd , mr/w , bc(3:0) output valid time from output clock t 1 cc ? 9ns ale, csx , rd/wr , rd , mr/w , bc(3:0) output hold time from output clock t 2 cc 0.0 ? ns ad(31:0) output valid ti me from output clock t 3 cc ? 9ns ad(31:0) output hold time from output clock t 4 cc 0.0 ? ns ad(31:0) input setup ti me to output clock t 5 sr 1.4 ? ns ad(31:0) input hold ti me from output clock t 6 sr 3 ? ns wait input setup time to output clock t 9 sr 12 ? ns wait input hold time from output clock t 10 sr 3 ? ns rmw output valid time from output clock t 11 cc ? 8ns rmw output hold time from output clock t 12 cc 1.3 ? ns ale width t 13 cc 8.5 ? ns ad(31:0) output ho ld time from rd/wr t 14 cc 0 ? ns
TC1115 electrical parameters data sheet 93 v1.0, 2005-02 advance information figure 4-13 write access in multiplexed access sdclko ad[31:0] address csx rd/wr mr/w cmdelay bc[3:0] t 3 t 1 t 1 t 4 t 2 t 1 t 2 t 2 read access write access t 7 t 8 mux_timing t 1 wait t 9 t 10 t 2 t 1 sdclko/ sdclki ad[31:0] address csx rd mr/w cmdelay bc[3:0] t 3 t 1 t 1 1 t 4 t 2 t 1 t 5 t 2 t 2 t 7 t 8 t 2 wait t 9 t 10 t 1 rmw t 11 t 12 t 4 t 3 t 6 data data address phase(s) address hold phase(s) command delay phase(s) (int.) command delay phase(s) (ext.) command phase(s) data hold phase(s) recovery phase(s) t 13 t 14 address phase(s) address hold phase(s) command delay phase(s) (int.) command delay phase(s) (ext.) command phase(s) recovery phase(s) t 13
TC1115 electrical parameters data sheet 94 v1.0, 2005-02 advance information 4.3.9 peripheral timings 4.3.9.1 ssc master mode timing (operating conditions apply; c l =50 pf) figure 4-14 ssc master mode timing parameter symbol limit values unit min. max. sclk clock period t 0 cc 2*t ssc 1) 1) t sscmin = t sys = 1/f sys . when f sys = 120mhz, t 0 = 16.7ns ?ns mtsr/slsox delay from sclk t 1 cc 0 8 ns mrst setup to sclk t 2 sr 10 ? ns mrst hold from sclk t 3 sr 5 ? ns ssc_tmg1 sclk 1)2) mtsr 1) t 1 t 1 mrst 1) t 3 data valid t 2 slsox 2) t 1 1) this timing is based on the following setup: con.ph = con.po = 0. 2) the transition at slsox is based on the following setup: ssotc.trail = 0 and the first sclk high pulse is in the first one of a transmission. t 0
TC1115 electrical parameters data sheet 95 v1.0, 2005-02 advance information 4.3.9.2 mli interface timing (operating conditions apply; c l =50 pf) figure 4-15 mli interface timing note: the generation of rreadyx is in th e input clock domain of the receiver. the reception of treadyx is asynchronous to tclkx. parameter symbol limit values unit min. max. tclk/rclk clock period t 0 cc/sr 2*t mli 1) 1) t mlimin = t sys = 1/f sys . when f sys = 120mhz, t 0 = 16.7ns ?ns mli outputs delay from tclk t 5 cc 0 8 ns mli inputs setup to rclk t 6 sr 4 ? ns mli inputs hold to rclk t 7 sr 4 ? ns rready output delay from tclk t 8 cc 0 8 ns mli _tmg1 tdatax tvalidx t 5 t 5 t 7 t 6 tclkx t 0 0.1 v ddp 0.9 v ddp rdatax rvalidx rclkx t 0 treadyx rreadyx t 8 t 8
TC1115 package outline data sheet 96 v1.0, 2005-02 advance information 5 package outline figure 5-1 p-lbga-208-2 package plastic package, p-lbga-208-2 (smd) (low profile ball y ou can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products. dimensions in mm smd = surface mounted device
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